Datasheet ATtiny2313, ATtiny2313V (Atmel) - 212

link to page 8 link to page 11 link to page 77 link to page 60 link to page 61 link to page 78 link to page 109 link to page 78 link to page 155 link to page 77 link to page 53 link to page 37 link to page 76 link to page 77 link to page 26 link to page 73 link to page 104 link to page 107 link to page 108 link to page 108 link to page 108 link to page 108 link to page 109 link to page 109 link to page 28 link to page 109 link to page 109 link to page 108 link to page 42 link to page 61 link to page 16 link to page 17 link to page 17 link to page 58 link to page 58 link to page 58 link to page 58 link to page 58 link to page 58 link to page 21 link to page 21 link to page 21 link to page 58 link to page 58 link to page 58 link to page 144 link to page 145 link to page 145 link to page 129 link to page 129 link to page 131 link to page 133 link to page 149 link to page 132 link to page 133 link to page 150 link to page 81
Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F (0x5F) SREG I T H S V N Z C 8 0x3E (0x5E) Reserved – – – – – – – – 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 0x3C (0x5C) OCR0B Timer/Counter0 – Compare Register B 77 0x3B (0x5B) GIMSK INT1 INT0 PCIE – – – – – 60 0x3A (0x5A) EIFR INTF1 INTF0 PCIF – – – – – 61 0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 78, 109 0x38 (0x58) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 78 0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN 155 0x36 (0x56) OCR0A Timer/Counter0 – Compare Register A 77 0x35 (0x55) MCUCR PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 53 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 37 0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 76 0x32 (0x52) TCNT0 Timer/Counter0 (8-bit) 77 0x31 (0x51) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 26 0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 73 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1BO – – WGM11 WGM10 104 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 107 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 108 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 108 0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte 108 0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte 108 0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte 109 0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte 109 0x27 (0x47) Reserved – – – – – – – – 0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 28 0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 109 0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 109 0x23 (0x43) GTCCR – – – – – – – PSR10 81 0x22 (ox42) TCCR1C FOC1A FOC1B – – – – – – 108 0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 42 0x20 (0x40) PCMSK PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 61 0x1F (0x3F) Reserved – – – – – – – – 0x1E (0x3E) EEAR – EEPROM Address Register 16 0x1D (0x3D) EEDR EEPROM Data Register 17 0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 17 0x1B (0x3B) PORTA – – – – – PORTA2 PORTA1 PORTA0 58 0x1A (0x3A) DDRA – – – – – DDA2 DDA1 DDA0 58 0x19 (0x39) PINA – – – – – PINA2 PINA1 PINA0 58 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 58 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 58 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 58 0x15 (0x35) GPIOR2 General Purpose I/O Register 2 21 0x14 (0x34) GPIOR1 General Purpose I/O Register 1 21 0x13 (0x33) GPIOR0 General Purpose I/O Register 0 21 0x12 (0x32) PORTD – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 58 0x11 (0x31) DDRD – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 58 0x10 (0x30) PIND – PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 58 0x0F (0x2F) USIDR USI Data Register 144 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 145 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 145 0x0C (0x2C) UDR UART Data Register (8-bit) 129 0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 129 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 131 0x09 (0x29) UBRRL UBRRH[7:0] 133 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 149 0x07 (0x27) Reserved – – – – – – – – 0x06 (0x26) Reserved – – – – – – – – 0x05 (0x25) Reserved – – – – – – – – 0x04 (0x24) Reserved – – – – – – – – 0x03 (0x23) UCSRC – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 132 0x02 (0x22) UBRRH – – – – UBRRH[11:8] 133 0x01 (0x21) DIDR – – – – – – AIN1D AIN0D 150 0x00 (0x20) Reserved – – – – – – – –
212 ATtiny2313
2543M–AVR–10/16 Document Outline Features Pin Configurations Overview Block Diagram Pin Descriptions VCC GND Port A (PA2..PA0) Port B (PB7..PB0) Port D (PD6..PD0) RESET XTAL1 XTAL2 General Information Resources Code Examples Data Retention AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register General Purpose Register File The X-register, Y- register, and Z-register Stack Pointer Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR ATtiny2313 Memories In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register The EEPROM Data Register – EEDR The EEPROM Control Register – EECR Atomic Byte Programming Split Byte Programming Erase Write Preventing EEPROM Corruption I/O Memory General Purpose I/O Registers General Purpose I/O Register 2 – GPIOR2 General Purpose I/O Register 1 – GPIOR1 General Purpose I/O Register 0 – GPIOR0 System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Clock Sources Default Clock Source Crystal Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock 128 kHz Internal Oscillator System Clock Prescalar CLKPR – Clock Prescale Register Power Management and Sleep Modes MCU Control Register – MCUCR Idle Mode Power-down Mode Standby Mode Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Watchdog Timer Control and Status Register - WDTCSR Interrupts Interrupt Vectors in ATtiny2313 I/O-Ports Introduction Ports as General Digital I/O Configuring the Pin Toggling the Pin Switching Between Input and Output Reading the Pin Value Digital Input Enable and Sleep Modes Alternate Port Functions MCU Control Register – MCUCR Alternate Functions of Port A Alternate Functions of Port B Alternate Functions of Port D Register Description for I/O-Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND External Interrupts Pin Change Interrupt Timing MCU Control Register – MCUCR General Interrupt Mask Register – GIMSK External Interrupt Flag Register – EIFR Pin Change Mask Register – PCMSK 8-bit Timer/Counter0 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A Timer/Counter Control Register B – TCCR0B Timer/Counter Register – TCNT0 Output Compare Register A – OCR0A Output Compare Register B – OCR0B Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source General Timer/Counter Control Register – GTCCR 16-bit Timer/Counter1 Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 Control Register C – TCCR1C Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B - OCR1BH and OCR1BL Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR USART Overview AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bit Sending Frames with 9 Data Bit Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA USART Control and Status Register B – UCSRB USART Control and Status Register C – UCSRC USART Baud Rate Registers – UBRRL and UBRRH Examples of Baud Rate Setting Universal Serial Interface – USI Overview Functional Descriptions Three-wire Mode SPI Master Operation Example SPI Slave Operation Example Two-wire Mode Start Condition Detector Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt USI Register Descriptions USI Data Register – USIDR USI Status Register – USISR USI Control Register – USICR Analog Comparator Analog Comparator Control and Status Register – ACSR Digital Input Disable Register – DIDR debugWIRE On- chip Debug System Features Overview Physical Interface Software Break Points Limitations of debugWIRE debugWIRE Related Register in I/O Memory debugWire Data Register – DWDR Self- Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Addressing the Flash During Self- Programming Store Program Memory Control and Status Register – SPMCSR EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software Preventing Flash Corruption Programming Time for Flash when Using SPM Memory Programming Program And Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Page Size Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Serial Programming Pin Mapping Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Extended Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics System and Reset Characteristics External Clock Drive Waveforms External Clock Drive Maximum Speed vs. VCC ATtiny2313 Typical Characteristics Active Supply Current Idle Supply Current Power-down Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 20P3 20S 20M1 Errata ATtiny2313 Rev C ATtiny2313 Rev B ATtiny2313 Rev A Datasheet Revision History Rev. 2543M – 10/16 Rev. 2543L – 08/10 Rev. 2543K – 03/10 Rev. 2543J – 11/09 Rev. 2543I – 04/06 Rev. 2543H – 02/05 Rev. 2543G – 10/04 Rev. 2543F – 08/04 Rev. 2543E – 04/04 Rev. 2543D – 03/04 Rev. 2543C – 12/03 Rev. 2543B – 09/03 Rev. 2543A