Datasheet LT3042 (Analog Devices) - 12

HerstellerAnalog Devices
Beschreibung20V, 200mA, Ultralow Noise, Ultrahigh PSRR RF Linear Regulator
Seiten / Seite32 / 12 — PIN FUNCTIONS IN (Pins 1, 2):. PGFB (Pin 6):. EN/UV (Pin 3):. SET (Pin …
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DokumentenspracheEnglisch

PIN FUNCTIONS IN (Pins 1, 2):. PGFB (Pin 6):. EN/UV (Pin 3):. SET (Pin 7):. PG (Pin 4):. ILIM (Pin 5):

PIN FUNCTIONS IN (Pins 1, 2): PGFB (Pin 6): EN/UV (Pin 3): SET (Pin 7): PG (Pin 4): ILIM (Pin 5):

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link to page 14 LT3042
PIN FUNCTIONS IN (Pins 1, 2):
Input. These pins supply power to the serves as a current monitoring pin with a 0V to 300mV regulator. The LT3042 requires a bypass capacitor at the range. If the programmable current limit functionality is IN pin. In general, a battery’s output impedance rises with not needed, tie ILIM to GND. A parasitic substrate diode frequency, so include a bypass capacitor in battery-powered exists between ILIM and GND pins of the LT3042; do not applications. While a 4.7µF input bypass capacitor gener- drive ILIM more than 0.3V below GND during normal ally suffices, applications with large load transients may operation or during a fault condition. require higher input capacitance to prevent input supply
PGFB (Pin 6):
Power Good Feedback. The PG pin pulls droop. Consult the Applications Information section on the proper use of an input capacitor and its effect on circuit high if PGFB increases beyond 300mV on its rising edge, performance, in particular PSRR. The LT3042 withstands with 7mV hysteresis on its falling edge. Connecting an reverse voltages on IN with respect to GND, OUTS and OUT. external resistor divider between OUT, PGFB and GND In the case of a reversed input, which occurs if a battery sets the programmable power good threshold with the is plugged-in backwards, the LT3042 acts as if a diode is following transfer function: 0.3V • (1 + RPG2/RPG1). As in series with its input. Hence, no reverse current flows discussed in the Applications Information section, PGFB into the LT3042 and no negative voltage appears at the also activates the fast start-up circuitry. Tie PGFB to IN load. The device protects itself and the load. if power good and fast start-up functionalities are not needed, and if reverse input protection is additionally
EN/UV (Pin 3):
Enable/UVLO. Pulling the LT3042’s EN/UV required, tie the anode of a 1N4148 diode to IN and its pin low places the part in shutdown. Quiescent current in cathode to PGFB. See the Typical Applications section for shutdown drops to less than 1µA and the output voltage details. A parasitic substrate diode exists between PGFB turns off. Alternatively, the EN/UV pin can set an input and GND pins of the LT3042; do not drive PGFB more supply undervoltage lockout (UVLO) threshold using a than 0.3V below GND during normal operation or during resistor divider between IN, EN/UV and GND. The LT3042 a fault condition. typically turns on when the EN/UV voltage exceeds 1.24V on its rising edge, with a 170mV hysteresis on its falling
SET (Pin 7):
SET. This pin is the inverting input of the error edge. The EN/UV pin can be driven above the input voltage amplifier and the regulation set-point for the LT3042. SET and maintain proper functionality. If unused, tie EN/UV to sources a precision 100µA current that flows through an IN. Do not float the EN/UV pin. external resistor connected between SET and GND. The LT3042’s output voltage is determined by V
PG (Pin 4):
Power Good. PG is an open-collector flag that SET = ISET • RSET. Output voltage range is from zero to 15V. Adding a capaci- indicates output voltage regulation. PG pulls low if PGFB tor from SET to GND improves noise, PSRR and transient is below 300mV. If the power good functionality is not response at the expense of increased start-up time. For needed, float the PG pin. A parasitic substrate diode exists optimum load regulation, Kelvin connect the ground side between PG and GND pins of the LT3042; do not drive of the SET pin resistor directly to the load. A parasitic PG more than 0.3V below GND during normal operation substrate diode exists between SET and GND pins of the or during a fault condition. LT3042; do not drive SET more than 0.3V below GND
ILIM (Pin 5):
Current Limit Programming Pin. Connecting during normal operation or during a fault condition. a resistor between ILIM and GND programs the current
GND (Pin 8, Exposed Pad Pin 11):
Ground. The exposed limit. For best accuracy, Kelvin connect this resistor directly backside is an electrical connection to GND. To ensure to the LT3042’s GND pin. The programming scale factor proper electrical and thermal performance, solder the is nominally 125mA•kΩ. The ILIM pin sources current exposed backside to the PCB ground and tie it directly to proportional (1:400) to output current; therefore, it also the GND pin. 3042fb 12 For more information www.linear.com/LT3042 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts