Datasheet AD8143 (Analog Devices) - 25

AD8143 Data Sheet OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE A COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-
Figure 49. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option
AD8143ACPZ-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 AD8143ACPZ-REEL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 AD8143ACPZ-REEL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 AD8143-EVALZ Evaluation Board 1 Z = RoHS Compliant Part.
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Rev. A | Page 24 of 24 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION OVERVIEW BASIC CLOSED-LOOP GAIN CONFIGURATIONS TERMINATING THE INPUT INPUT CLAMPING PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Minimizing Parasitic Reactances in the Feedback Network Maximizing Heat Removal DRIVING A CAPACITIVE LOAD POWER-DOWN COMPARATORS SYNC PULSE EXTRACTION USING COMPARATORS OUTLINE DIMENSIONS ORDERING GUIDE