Datasheet CD4070BMS, CD4077BMS (Intersil) - 6
| Hersteller | Intersil |
| Beschreibung | CMOS Quad Exclusive OR and Exclusive NOR Gates |
| Seiten / Seite | 8 / 6 — Schematics. VDD. 2 (5, 9, 12). TRUTH TABLE CD4070BMS. 1 OF 4 GATES. VSS. … |
| Revision | 2017-12-22 |
| Dateiformat / Größe | PDF / 271 Kb |
| Dokumentensprache | Englisch |
Schematics. VDD. 2 (5, 9, 12). TRUTH TABLE CD4070BMS. 1 OF 4 GATES. VSS. 3 (4, 10, 11). 1 (6, 8, 13). * ALL INPUTS PROTECTED BY
Modelllinie für dieses Datenblatt
Textversion des Dokuments
CD4070BMS, CD4077BMS
Schematics VDD p VDD B* 2 (5, 9, 12) n n p p TRUTH TABLE CD4070BMS 1 OF 4 GATES VSS A B J p VDD p J
0 0 0 1 0 1
3 (4, 10, 11) p n n
0 1 1
A*
1 1 0
1 (6, 8, 13) n
1 = High Level
VDD
0 = Low Level J = AB
VSS VSS * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070BMS (1 OF 4 IDENTICAL GATES) VDD VDD p p B* 2 (5, 9, 12) n n n p TRUTH TABLE CD4077BMS 1 OF 4 GATES VSS A B J p VDD J
0 0 1 1 0 0
3 (4, 10, 11) p n n
0 1 0
A*
1 1 1
1 (6, 8, 13) n
1 = High Level
VDD
0 = Low Level J = AB
VSS VSS * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077BMS (1 OF 4 IDENTICAL GATES)
FN3322 Rev 0.00 Page 6 of 8 December 1992
Schematics VDD p VDD B* 2 (5, 9, 12) n n p p TRUTH TABLE CD4070BMS 1 OF 4 GATES VSS A B J p VDD p J
0 0 0 1 0 1
3 (4, 10, 11) p n n
0 1 1
A*
1 1 0
1 (6, 8, 13) n
1 = High Level
VDD
0 = Low Level J = AB
VSS VSS * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070BMS (1 OF 4 IDENTICAL GATES) VDD VDD p p B* 2 (5, 9, 12) n n n p TRUTH TABLE CD4077BMS 1 OF 4 GATES VSS A B J p VDD J
0 0 1 1 0 0
3 (4, 10, 11) p n n
0 1 0
A*
1 1 1
1 (6, 8, 13) n
1 = High Level
VDD
0 = Low Level J = AB
VSS VSS * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077BMS (1 OF 4 IDENTICAL GATES)
FN3322 Rev 0.00 Page 6 of 8 December 1992