Datasheet ADIS16364 (Analog Devices) - 10

link to page 10 link to page 10 link to page 10 link to page 11 link to page 10 link to page 10 link to page 11 link to page 10 link to page 10
Data Sheet ADIS16364 THEORY OF OPERATION BASIC OPERATION
The user registers provide addressing for all input/output The ADIS16364 is an autonomous sensor system that starts up operations on the SPI interface. Each 16-bit register has two after it has a valid power supply voltage and begins producing 7-bit addresses: one for its upper byte and one for its lower inertial measurement data at the factory default sample rate byte. Table 8 lists the lower byte address for each register, and setting of 819.2 SPS. After each sample cycle, the sensor data is Figure 10 shows the generic bit assignments. loaded into the output registers, and DIO1 pulses high, which
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
provides a new data ready control signal for driving system-level 010 interrupt service routines. In a typical system, a master processor
UPPER BYTE LOWER BYTE
07906- accesses the output data registers through the SPI interface, using Figure 10. Generic Register Bit Assignments the connection diagram shown in Figure 9. Table 6 provides a
READING SENSOR DATA
generic functional description for each pin on the master pro- Although the ADIS16364 produces data independently, it cessor. Table 7 describes the typical master processor settings operates as a SPI slave device that communicates with system that are normally found in a configuration register and used for (master) processors using the 16-bit segments displayed in communicating with the ADIS16364. Figure 11. Individual register reads require two of these 16-bit
I/O LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS
sequences. The first 16-bit sequence contains the read command
5V VDD
bit (R/W = 0) and the target register address (A6 to A0); the last eight bits are “don’t care” bits when requesting a read. The second
10 11 12 SYSTEM
16-bit sequence transmits the register contents (D15 to D0) on
PROCESSOR SS 6 CS ADIS16364 SPI MASTER
the DOUT line. For example, if DIN = 0x0A00, the contents of
SPI SLAVE SCLK 3 SCLK
the XACCL_OUT register are shifted out on the DOUT line
MOSI 5 DIN
during the next 16-bit sequence.
MISO 4 DOUT
The SPI operates in ful -duplex mode, which means that the master
IRQ 7 DIO1
processor can read the output data from DOUT while using the
13 14 15
same SCLK pulses to transmit the next target address on DIN. 009 07906-
DEVICE CONFIGURATION
Figure 9. Electrical Connection Diagram The user register memory map (see Table 8) identifies configu-
Table 6. Generic Master Processor Pin Names and Functions
ration registers as either read/write or write only. Configuration
Pin Name Function
commands also use the bit sequence shown in Figure 11. If the SS Slave select MSB = 1, the last eight bits (DC7 to DC0) in the DIN sequence SCLK Serial clock are loaded into the memory address associated with the address MOSI Master output, slave input bits (A6 to A0). For example, if DIN = 0xA11F, 0x1F is loaded MISO Master input, slave output into Address 0x21 (XACCL_OFF, upper byte) at the conclusion IRQ Interrupt request of the data frame. The master processor initiates the backup function by setting
Table 7. Generic Master Processor SPI Settings
GLOB_CMD[3] = 1 (DIN = 0xBE08). This command copies
Processor Setting Description
the user registers into their assigned flash memory locations Master The ADIS16364 operates as a slave and requires the power supply to stay within its normal operating SCLK Rate ≤ 2 MHz1 Normal mode, SMPL_PRD[7:0] ≤ 0x09 range for the entire 50 ms process. The FLASH_CNT register SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase) provides a running count of these events for monitoring the MSB First Mode Bit sequence long-term reliability of the flash memory. 16-Bit Mode Shift register/data length 1 For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
CS SCLK DIN R/W R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 A6 A5 DOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 NOTES 1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
011
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0. 2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
07906- Figure 11. SPI Communication Bit Sequence Rev. E | Page 9 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Operation Reading Sensor Data Device Configuration Memory Map Burst Read Data Collection Output Data Registers Calibration Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) Operational Control Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range Input/Output Functions General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Installation/Handling Gyroscope Bias Optimization Input ADC Channel Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide