Datasheet ADXL346 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 3-Axis, ±2 g/±4 g/±8 g/±16 g Ultralow Power Digital Accelerometer |
| Seiten / Seite | 41 / 3 — ADXL346. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 6/15—Rev. B to … |
| Revision | C |
| Dateiformat / Größe | PDF / 793 Kb |
| Dokumentensprache | Englisch |
ADXL346. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 6/15—Rev. B to Rev. C. 5/11—Rev. A to Rev. B. 11/10—Rev. 0 to Rev. A
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ADXL346 Data Sheet TABLE OF CONTENTS
Features .. 1 Register Definitions ... 23 Applications ... 1 Applications Information .. 29 General Description ... 1 Power Supply Decoupling ... 29 Functional Block Diagram .. 1 Mechanical Considerations for Mounting .. 29 Revision History ... 2 Tap Detection .. 29 Specifications ... 3 Improved Tap Detection .. 30 Absolute Maximum Ratings .. 5 Tap Sign ... 30 Thermal Resistance .. 5 Threshold .. 31 Package Information .. 5 Link Mode ... 31 ESD Caution .. 5 Sleep Mode vs. Low Power Mode... 31 Pin Configuration and Function Descriptions ... 6 Offset Calibration ... 31 Typical Performance Characteristics ... 7 Using Self-Test .. 32 Theory of Operation .. 12 Orientation Sensing ... 32 Power Sequencing .. 12 Data Formatting of Upper Data Rates ... 34 Power Savings ... 13 Noise Performance ... 35 Serial Communications ... 14 Operation at Voltages Other Than 2.6 V .. 36 SPI ... 14 Offset Performance at Lowest Data Rates ... 36 I2C ... 17 Axes of Acceleration Sensitivity ... 37 Interrupts ... 19 Layout and Design Recommendations ... 38 FIFO ... 20 Outline Dimensions ... 39 Self-Test .. 21 Ordering Guide .. 39 Register Map .. 22
REVISION HISTORY 6/15—Rev. B to Rev. C
Changes to Features Section and General Description Section .. 1 Change to Figure 36 ... 14 Change to FIFO Section .. 20
5/11—Rev. A to Rev. B
Added Endnote 7 .. 3 Added Preventing Bus Traffic Errors Section ... 14 Changes to Figure 37, Figure 38, Figure 39 ... 15 Changes to Table 12 .. 18 Changes to Using Self-Test Section .. 32 Changes to Axes of Acceleration Sensitivity Section ... 37
11/10—Rev. 0 to Rev. A
Changes to Ordering Guide .. 39
5/10—Revision 0: Initial Version
Rev. C | Page 2 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE PACKAGE INFORMATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING POWER SAVINGS Power Modes Autosleep Mode Standby Mode SERIAL COMMUNICATIONS SPI Preventing Bus Traffic Errors I2C INTERRUPTS DATA_READY Bit SINGLE_TAP Bit DOUBLE_TAP Bit Activity Bit Inactivity Bit FREE_FALL Bit Watermark Bit Overrun Bit Orientation Bit FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO SELF-TEST REGISTER MAP REGISTER DEFINITIONS Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Improved Tap Bit Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Register 0x3A—TAP_SIGN (Read Only) xSIGN Bits xTAP Bits Register 0x3B—ORIENT_CONF (Read/Write) INT_ORIENT Bit Dead Zone Bits INT_3D Bit Divisor Bits Register 0x3C—Orient (Read Only) Vx Bits xD_ORIENT Bits APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING MECHANICAL CONSIDERATIONS FOR MOUNTING TAP DETECTION IMPROVED TAP DETECTION TAP SIGN THRESHOLD LINK MODE SLEEP MODE VS. LOW POWER MODE OFFSET CALIBRATION USING SELF-TEST ORIENTATION SENSING DATA FORMATTING OF UPPER DATA RATES NOISE PERFORMANCE OPERATION AT VOLTAGES OTHER THAN 2.6 V OFFSET PERFORMANCE AT LOWEST DATA RATES AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
ADXL346 Data Sheet TABLE OF CONTENTS
Features .. 1 Register Definitions ... 23 Applications ... 1 Applications Information .. 29 General Description ... 1 Power Supply Decoupling ... 29 Functional Block Diagram .. 1 Mechanical Considerations for Mounting .. 29 Revision History ... 2 Tap Detection .. 29 Specifications ... 3 Improved Tap Detection .. 30 Absolute Maximum Ratings .. 5 Tap Sign ... 30 Thermal Resistance .. 5 Threshold .. 31 Package Information .. 5 Link Mode ... 31 ESD Caution .. 5 Sleep Mode vs. Low Power Mode... 31 Pin Configuration and Function Descriptions ... 6 Offset Calibration ... 31 Typical Performance Characteristics ... 7 Using Self-Test .. 32 Theory of Operation .. 12 Orientation Sensing ... 32 Power Sequencing .. 12 Data Formatting of Upper Data Rates ... 34 Power Savings ... 13 Noise Performance ... 35 Serial Communications ... 14 Operation at Voltages Other Than 2.6 V .. 36 SPI ... 14 Offset Performance at Lowest Data Rates ... 36 I2C ... 17 Axes of Acceleration Sensitivity ... 37 Interrupts ... 19 Layout and Design Recommendations ... 38 FIFO ... 20 Outline Dimensions ... 39 Self-Test .. 21 Ordering Guide .. 39 Register Map .. 22
REVISION HISTORY 6/15—Rev. B to Rev. C
Changes to Features Section and General Description Section .. 1 Change to Figure 36 ... 14 Change to FIFO Section .. 20
5/11—Rev. A to Rev. B
Added Endnote 7 .. 3 Added Preventing Bus Traffic Errors Section ... 14 Changes to Figure 37, Figure 38, Figure 39 ... 15 Changes to Table 12 .. 18 Changes to Using Self-Test Section .. 32 Changes to Axes of Acceleration Sensitivity Section ... 37
11/10—Rev. 0 to Rev. A
Changes to Ordering Guide .. 39
5/10—Revision 0: Initial Version
Rev. C | Page 2 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE PACKAGE INFORMATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING POWER SAVINGS Power Modes Autosleep Mode Standby Mode SERIAL COMMUNICATIONS SPI Preventing Bus Traffic Errors I2C INTERRUPTS DATA_READY Bit SINGLE_TAP Bit DOUBLE_TAP Bit Activity Bit Inactivity Bit FREE_FALL Bit Watermark Bit Overrun Bit Orientation Bit FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO SELF-TEST REGISTER MAP REGISTER DEFINITIONS Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Improved Tap Bit Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Register 0x3A—TAP_SIGN (Read Only) xSIGN Bits xTAP Bits Register 0x3B—ORIENT_CONF (Read/Write) INT_ORIENT Bit Dead Zone Bits INT_3D Bit Divisor Bits Register 0x3C—Orient (Read Only) Vx Bits xD_ORIENT Bits APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING MECHANICAL CONSIDERATIONS FOR MOUNTING TAP DETECTION IMPROVED TAP DETECTION TAP SIGN THRESHOLD LINK MODE SLEEP MODE VS. LOW POWER MODE OFFSET CALIBRATION USING SELF-TEST ORIENTATION SENSING DATA FORMATTING OF UPPER DATA RATES NOISE PERFORMANCE OPERATION AT VOLTAGES OTHER THAN 2.6 V OFFSET PERFORMANCE AT LOWEST DATA RATES AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE