Datasheet LTC4318 (Analog Devices) - 5

HerstellerAnalog Devices
BeschreibungDual I2C/SMBus Address Translator
Seiten / Seite16 / 5 — Typical perForMance characTerisTics. TA = 25°C, VCC = 3.3V unless …
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Typical perForMance characTerisTics. TA = 25°C, VCC = 3.3V unless otherwise noted. SDAOUT Fall Delay vs Bus

Typical perForMance characTerisTics TA = 25°C, VCC = 3.3V unless otherwise noted SDAOUT Fall Delay vs Bus

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LTC4318
Typical perForMance characTerisTics TA = 25°C, VCC = 3.3V unless otherwise noted. SDAOUT Fall Delay vs Bus SDAOUT Fall Time vs SDAOUT Fall Time vs Bus Capacitance Temperature Capacitance
300 120 120 C = 100pF 275 100 100 250 V V CC = 5V CC = 5V VCC = 5V (ns) 225 VCC = 3.3V (ns) 80 (ns) 80 200 VCC = 2.25V VCC = 3.3V VCC = 3.3V 175 60 60 t f(SDAOUT) t f(SDAOUT) t PDHL(SDAOUT) 150 40 V V 40 CC = 2.25V CC = 2.25V 125 100 20 20 0 200 400 600 800 1000 –50 –25 0 25 50 75 100 0 200 400 600 800 1000 CBUS (pF) TEMPERATURE (°C) CBUS (pF) 4318 G07 4318 G08 4318 G09
pin FuncTions XORL1/XORL2:
Translator XOR Lower Nibble Configura- to SCLOUT. Connect a pull-up resistor, typically 10k, from tion Input. The DC voltage at this pin configures the lower this pin to the bus pull-up supply. Leave open or tie to 4-bit nibble of the address translation byte. Tie the pin to GND if unused. an external resistive divider connected between VCC and
SCLIN1/SCLIN2:
Input Bus Clock Input and Output. Con- GND to set the desired DC voltage. nect this pin to the SCL line on the master side. An external
XORH1/XORH2:
Translator XOR Upper Nibble Configura- pull-up resistor or current source is required. Connect to tion Input. The DC voltage at this pin configures the upper VCC through a pull-up resistor if unused. 3-bit nibble of the address translation byte. Tie the pin to
SCLOUT1/SCLOUT2:
Output Bus Clock Input and Output. an external resistive divider connected between VCC and Connect this pin to the SCL line on the slave side. An external GND to set the desired DC voltage. Connect this pin to VCC pull-up resistor or current source is required. Connect to to activate pass-through mode. See Application Informa- V tion section for more details. CC through a pull-up resistor if unused.
SDAIN1/SDAIN2:
Input Bus Data Input and Output. Connect
ENABLE1/ENABLE2:
Enable Input. If ENABLE pin is low, this pin to the SDA line on the master side. An external the address translation is disabled, SDAIN is disconnected pull-up resistor or current source is required. Connect to from SDAOUT, and SCLIN is disconnected from SCLOUT. V A low to high transition on ENABLE restarts the configura- CC through a pull-up resistor if unused. tion of the address translation byte and also enables the
SDAOUT1/SDAOUT2:
Output Bus Data Input and Output. address translation. Connect to VCC if unused. Connect this pin to the SDA line on the slave side. An external pull-up resistor or current source is required.
Exposed Pad:
Exposed pad may be left open or connected Connect to V to device GND. CC through a pull-up resistor if unused.
V GND:
Device Ground.
CC:
Power Supply Input (2.25V to 5.5V). If the supply voltages for the input and output buses are different, con-
READY1/READY2:
Ready Status Output. This is an open nect this pin to the lower supply. If the input and output drain output to indicate that the device is ready for address supplies have the same nominal value and with tolerance translation. The pin releases high when the LTC4318 has less than or equal to ±10%, connect VCC to either supply. completed configuration of the address translation byte, Bypass with at least 0.1µF to GND. SDAIN is connected to SDAOUT and SCLIN is connected 4318fa For more information www.linear.com/LTC4318 5