Datasheet MCP6021, MCP601R, MCP602, MCP603, MCP604 (Microchip) - 17

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MCP6021/1R/2/3/4 4.0 APPLICATIONS INFORMATION
VDD The MCP6021/1R/2/3/4 family of operational amplifiers is fabricated on Microchip’s state-of-the-art CMOS process. The amplifiers are unity-gain stable and suitable D1 D2 U1 for a wide range of general purpose applications. V1
4.1 Rail-to-Rail Input MCP602X
VOUT V2 4.1.1 PHASE REVERSAL The MCP6021/1R/2/3/4 operational amplifiers are
FIGURE 4-2:
Protecting the Analog Inputs. designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-42 shows the 4.1.3 INPUT CURRENT LIMITS input voltage exceeding the supply voltage without any phase reversal. In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at 4.1.2 INPUT VOLTAGE LIMITS the input pins. See the Absolute Maximum Ratings† section. Figure 4-3 shows one approach to protecting In order to prevent damage and/or improper operation these inputs. The resistors, R of these amplifiers, the circuit must limit the voltages at 1 and R2, limit the pos- sible currents in or out of the input pins (and the ESD the input pins. See the Absolute Maximum Ratings† diodes, D section. 1 and D2). The diode currents will go through either VDD or VSS. The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize Input Bias VDD (IB) current. D1 D2 U1 Bond V1 VDD V Pad R OUT 1
MCP602X
V2 R2 Bond Input Bond VIN+ VIN Pad Stage Pad VSS – min (V1,V2) min(R1,R2) > 2 mA max(V1,V2) – VDD min(R1,R2) > Bond 2 mA VSS Pad
FIGURE 4-3:
Protecting the Analog Inputs.
FIGURE 4-1:
Simplified Analog Input ESD 4.1.4 NORMAL OPERATION Structures. The input stage of the MCP6021/1R/2/3/4 operational The input ESD diodes clamp the inputs when they try amplifiers uses two differential CMOS input stages in to go more than one diode drop below VSS. They also parallel. One operates at a low Common-Mode Voltage clamp any voltages that go well above VDD. Their (V breakdown voltage is high enough to allow normal CM) input, while the other operates at high VCM. With this topology, the device operates with V operation, but not low enough to protect against slow CM up to 0.3V above V overvoltage (beyond V DD and 0.3V below VSS. DD) events. Very fast ESD events (that meet the specifications) are limited so that damage does not occur. In some applications, it may
4.2 Rail-to-Rail Output
be necessary to prevent excessive voltages from The maximum output voltage swing is the maximum reaching the operational amplifier inputs. Figure 4-2 swing possible under a particular output load. According shows one approach to protecting these inputs. to the specification table, the output can reach within A significant amount of current can flow out of the 20 mV of either supply rail when RL = 10 k. See inputs when the Common-Mode Voltage (V Figure 2-31 and Figure 2-34 for more information CM) is below ground (V concerning typical performance. SS). See Figure 2-42.  2001-2017 Microchip Technology Inc. DS20001685E-page 17 Document Outline Features Applications Design Aids Typical Application Description Package Types 1.0 Electrical Characteristics Absolute Maximum Ratings† DC Electrical Characteristics AC Electrical Characteristics MCP6023 Chip Select (CS) Electrical Characteristics Temperature Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6023. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage (Industrial Temperature Parts). FIGURE 2-2: Input Offset Voltage (Extended Temperature Parts). FIGURE 2-3: Input Offset Voltage vs. Common-Mode Input Voltage with VDD = 2.5V. FIGURE 2-4: Input Offset Voltage Drift (Industrial Temperature Parts). FIGURE 2-5: Input Offset Voltage Drift (Extended Temperature Parts). FIGURE 2-6: Input Offset Voltage vs. Common-Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Temperature. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: Input Offset Voltage vs. Output Voltage. FIGURE 2-11: Input Noise Voltage Density vs. Common-Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Common-Mode Input Voltage. FIGURE 2-14: Quiescent Current vs. Supply Voltage. FIGURE 2-15: Output Short-Circuit Current vs. Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Temperature. FIGURE 2-17: Quiescent Current vs. Temperature. FIGURE 2-18: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-19: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-20: Small Signal DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-22: DC Open-Loop Gain vs. Temperature. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Common-Mode Input Voltage. FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Output Voltage. FIGURE 2-25: Slew Rate vs. Temperature. FIGURE 2-26: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 1 kHz. FIGURE 2-27: The MCP6021/1R/2/3/4 Family Shows No Phase Reversal Under Overdrive. FIGURE 2-28: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-29: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 20 kHz. FIGURE 2-30: Channel-to-Channel Separation vs. Frequency (MCP6022 and MCP6024 only). FIGURE 2-31: Output Voltage Headroom vs. Output Current. FIGURE 2-32: Small Signal Non-Inverting Pulse Response. FIGURE 2-33: Large Signal Non-Inverting Pulse Response. FIGURE 2-34: Output Voltage Headroom vs. Temperature. FIGURE 2-35: Small Signal Inverting Pulse Response. FIGURE 2-36: Large Signal Inverting Pulse Response. FIGURE 2-37: VREF Accuracy vs. Supply Voltage (MCP6021 and MCP6023 only). FIGURE 2-38: Chip Select (CS) Hysteresis (MCP6023 only) with VDD = 2.5V. FIGURE 2-39: Chip Select (CS) to Amplifier Output Response Time (MCP6023 Only). FIGURE 2-40: VREF Accuracy vs. Temperature (MCP6021 and MCP6023 only). FIGURE 2-41: Chip Select (CS) Hysteresis (MCP6023 only) with VDD = 5.5V. FIGURE 2-42: Measured Input Current vs. Input Voltage (Below VSS) 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Reference Voltage (VREF) MCP6021 and MCP6023 3.4 Chip Select Digital Input (CS) 3.5 Power Supply (VSS and VDD) 4.0 Applications Information 4.1 Rail-to-Rail Input 4.1.1 Phase Reversal 4.1.2 Input Voltage Limits FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.1.3 Input Current Limits FIGURE 4-3: Protecting the Analog Inputs. 4.1.4 Normal Operation 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO, Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Gain Peaking FIGURE 4-6: Non-Inverting Gain Circuit with Parasitic Capacitance. FIGURE 4-7: Non-Inverting Gain Circuit with Parasitic Capacitance. 4.5 MCP6023 Chip Select (CS) 4.6 MCP6021 and MCP6023 Reference Voltage FIGURE 4-8: Simplified Internal VREF Circuit (MCP6021 and MCP6023 only). FIGURE 4-9: Non-Inverting Gain Circuit Using VREF (MCP6021 and MCP6023 only). FIGURE 4-10: Inverting Gain Circuit Using VREF (MCP6021 and MCP6023 only). 4.7 Supply Bypass 4.8 Unused Operational Amplifiers FIGURE 4-11: Unused Operational Amplifiers. 4.9 PCB Surface Leakage FIGURE 4-12: Example Guard Ring Layout. 4.10 High-Speed PCB Layout 4.11 Typical Applications 4.11.1 A/D Converter Driver and Anti-Aliasing Filter FIGURE 4-13: A/D Converter Driver and Anti-Aliasing Filter with a 20 kHz Cutoff Frequency. 4.11.2 Optical Detector Amplifier FIGURE 4-14: Transimpedance Amplifier for an Optical Detector. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MPLAB® Mindi™ Analog Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) APPENDIX A: Revision History Revision E (January 2017) Revision D (February 2009) Revision C (December 2005) Revision B (November 2003) Revision A (November 2001) Product Identification System Worldwide Sales and Service