Datasheet AD7888 (Analog Devices) - 10

HerstellerAnalog Devices
Beschreibung2.7 V to 5.25 V, Micro Power, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Pin TSSOP
Seiten / Seite18 / 10 — AD7888. TYPICAL CONNECTION DIAGRAM. SUPPLY 2.7V. TO 5.25V. 0.1. SERIAL …
RevisionC
Dateiformat / GrößePDF / 246 Kb
DokumentenspracheEnglisch

AD7888. TYPICAL CONNECTION DIAGRAM. SUPPLY 2.7V. TO 5.25V. 0.1. SERIAL INTERFACE. VDD. REF IN/. REF OUT. AIN1. SCLK. 0V TO. –65. AIN2. DOUT

AD7888 TYPICAL CONNECTION DIAGRAM SUPPLY 2.7V TO 5.25V 0.1 SERIAL INTERFACE VDD REF IN/ REF OUT AIN1 SCLK 0V TO –65 AIN2 DOUT

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AD7888 TYPICAL CONNECTION DIAGRAM
For ac applications, removing high frequency components from Figure 8 shows a typical connection diagram for the AD7888. the analog input signal is recommended by use of an RC low- Both AGND pins are connected to the analog ground plane of pass filter on the relevant analog input pin. In applications the system. V where harmonic distortion and signal to noise ratio are critical REF is connected to a well decoupled VDD pin to provide an analog input range of 0 V to VDD. The conversion the analog input should be driven from a low impedance source. result is output in a 16-bit word with four leading zeroes fol- Large source impedances will significantly affect the ac perfor- lowed by the MSB of the 12-bit result. For applications where mance of the ADC. This may necessitate the use of an input power consumption is of concern, the automatic power down at buffer amplifier. The choice of the op amp will be a function of the end of conversion should be used to improve power perfor- the particular application. mance. See Modes of Operation section of the data sheet. When no amplifier is used to drive the analog input the source impedance should be limited to low values. The maximum
SUPPLY 2.7V TO 5.25V
source impedance will depend on the amount of total harmonic
10

F 0.1

F
distortion (THD) that can be tolerated. The THD will increase
SERIAL INTERFACE
as the source impedance increases and performance will degrade.
VDD REF IN/
Figure 10 shows a graph of the total harmonic distortion versus
REF OUT
analog input signal frequency for different source impedances.
AD7888 AIN1 SCLK 0V TO –65 AIN2 REF IN/ DOUT THD vs. FREQUENCY FOR DIFFERENT REF OUT

C/

P SOURCE IMPEDANCES INPUT AIN8 DIN –70 VDD = 5V 5V EXT REFERENCE AGND CS RIN = 1k

, CIN = 100pF AGND –75 dB – RIN = 50

, CIN = 2.2nF
Figure 8. Typical Connection Diagram
THD –80 Analog Input
Figure 9 shows an equivalent circuit of the analog input structure of the AD7888. The two diodes D1 and D2 provide ESD pro-
–85
tection for the analog inputs. Care must be taken to ensure that
R
the analog input signal never exceeds the supply rails by more
IN = 10

, CIN = 10nF –90
than 200 mV. This will cause these diodes to become forward-
0.15 10.89 21.14 31.59 42.14 49.86
biased and start conducting current into the substrate. 20 mA is
INPUT FREQUENCY – kHz
the maximum current these diodes can conduct without causing Figure 10. THD vs. Analog Input Frequency irreversible damage to the part. However, it is worth noting that
Analog Input Selection
a small amount of current (1 mA) being conducted into the On power-up, the default AIN selection is AIN1. When returning substrate due to an overvoltage on an unselected channel, can to normal operation from power-down, the AIN selected will be cause inaccurate conversions on a selected channel. The capaci- the same one that was selected prior to power-down being initi- tor C1 in Figure 9 is typically about 4 pF and can primarily be ated. Table II below shows the multiplexer address correspond- attributed to pin capacitance. The resistor R1 is a lumped com- ing to each analog input from AIN1 to AIN8 for the AD7888. ponent made up of the on resistance of a multiplexer and a switch. This resistor is typically about 100 Ω. The capacitor C2 is the
Table II. Channel Configurations
ADC sampling capacitor and has a capacitance of 20 pF typically. Note: The analog input capacitance seen when the track and
ADD2 ADD1 ADD0 Analog Input Channel
hold is in track mode is typically 38 pF, while in hold mode it is 0 0 0 AIN1 typically 4 pF. 0 0 1 AIN2 0 1 0 AIN3
VDD
0 1 1 AIN4 1 0 0 AIN5
D1 C2
1 0 1 AIN6
R1 20pF V
1 1 0 AIN7
IN C1
1 1 1 AIN8
D2 4pF CONVERSION PHASE – SWITCH OPEN TRACK PHASE – SWITCH CLOSED On-Chip Reference
The AD7888 has an on-chip 2.5 V reference. This reference can Figure 9. Equivalent Analog Input Circuit be enabled or disabled by clearing or setting the REF bit in the Control Register, respectively. If the on-chip reference is to be used externally in a system, it must be buffered before it is applied elsewhere. If an external reference is applied to the device, the internal reference is automatically overdriven. However, in REV. C –9–