Datasheet AD9235 (Analog Devices) - 4

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Data Sheet AD9235 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted.
Table 1. Test AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 12 12 12 Bits ACCURACY No Missing Codes Guaranteed Full VI 12 12 12 Bits Offset Error Full VI ±0.30 ±1.20 ±0.50 ±1.20 ±0.50 ±1.20 % FSR Gain Error1 Full VI ±0.30 ±2.40 ±0.50 ±2.50 ±0.50 ±2.60 % FSR Differential Nonlinearity (DNL)2 Full IV ±0.35 ±0.65 ±0.35 ±0.75 ±0.40 ±0.80 LSB 25°C I ±0.35 ±0.35 ±0.35 LSB Integral Nonlinearity (INL)2 Full IV ±0.45 ±0.80 ±0.50 ±0.90 ±0.70 ±1.30 LSB 25°C I ±0.40 ±0.40 ±0.45 LSB TEMPERATURE DRIFT Offset Error Full V ±2 ±2 ±3 ppm/°C Gain Error Full V ±12 ±12 ±12 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV INPUT REFERRED NOISE VREF = 0.5 V 25°C V 0.54 0.54 0.54 LSB rms VREF = 1.0 V 25°C V 0.27 0.27 0.27 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V Full IV 1 1 1 V p-p Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p Input Capacitance3 Full V 7 7 7 pF REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ POWER SUPPLIES Supply Voltages AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V Supply Current IAVDD2 Full V 30 55 100 mA IDRVDD2 Full V 2 5 7 mA PSRR Full V ±0.01 ±0.01 ±0.01 % FSR POWER CONSUMPTION DC Input4 Full V 90 165 300 mW Sine Wave Input2 Full VI 95 110 180 205 320 350 mW Standby Power5 Full V 1.0 1.0 1.0 mW 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate, fIN = 2.4 MHz, ful -scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND). Rev. D | Page 3 of 40 Document Outline Specifications DC Specifications Digital Specifications Switching Specifications AC Specifications Absolute Maximum Ratings Explanation of Test Levels ESD Caution Pin Configurations and Function Descriptions Definitions of Specifications Equivalent Circuits Typical Performance Characteristics Applying the AD9235 Theory of Operation Analog Input Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection TSSOP Evaluation Board LFCSP Evaluation Board Outline Dimensions Ordering Guide