Datasheet AD7866 (Analog Devices) - 4

HerstellerAnalog Devices
BeschreibungDual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
Seiten / Seite25 / 4 — AD7866. Parameter. A Version1. B Version1. Unit. Test Conditions/Comments
RevisionA
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DokumentenspracheEnglisch

AD7866. Parameter. A Version1. B Version1. Unit. Test Conditions/Comments

AD7866 Parameter A Version1 B Version1 Unit Test Conditions/Comments

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AD7866 Parameter A Version1 B Version1 Unit Test Conditions/Comments
CONVERSION RATE Conversion Time 16 16 SCLK cycles 800 ns with SCLK = 20 MHz Track/Hold Acquisition Time3 300 300 ns max Throughput Rate 1 1 MSPS max See Serial Interface Section POWER REQUIREMENTS VDD 2.7/5.25 2.7/5.25 V min/max VDRIVE 2.7/5.25 2.7/5.25 V min/max I 7 DD Digital I/Ps = 0 V or VDRIVE Normal Mode (Static) 3.1 3.1 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA Typical if Using Internal Reference. 2.8 2.8 mA max VDD = 2.7 V to 3.6 V. Add 0.35 mA Typical if Using Internal Reference. Operational, fS = 1 MSPS 4.8 4.8 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA Typical if Using Internal Reference. 3.8 3.8 mA max VDD = 2.7 V to 3.6 V. Add 0.5 mA Typical if Using Internal Reference. Partial Power-Down Mode 1.6 1.6 mA max fS = 100 kSPS, fSCLK = 20 MHz Add 0.2 mA Typ if Using Internal Reference. Partial Power-Down Mode 560 560 µA max (Static) Add 100 µA Typical if Using Internal Reference. Full Power-Down Mode 1 1 µA max SCLK On or Off. TA = –40C to +85C 2 2 µA max SCLK On or Off. 85C < TA ≤ 125C Power Dissipation7 Normal Mode (Operational) 24 24 mW max VDD = 5 V 11.4 11.4 mW max VDD = 3 V Partial Power-Down (Static) 2.8 2.8 mW max VDD = 5 V. SCLK On or Off. 1.68 1.68 mW max VDD = 3 V. SCLK On or Off. Full Power-Down (Static) 5 5 µW max VDD = 5 V. SCLK On or Off. 3 3 µW max VDD = 3 V. SCLK On or Off. NOTES 1Temperature ranges as follows: A, B Versions: –40°C to +125°C. 2See Terminology section. 3Sample tested @ 25°C to ensure compliance. 4External reference range that may be applied at VREF, DCAPA, or DCAPB. 5Relates to pins VREF, DCAPA, or DCAPB. 6See Reference section for DCAPA, DCAPB output impedances. 7See Power vs. Throughput Rate section. Specifications subject to change without notice. REV. A –3– Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Zero Code Error Zero Code Error Match Positive Gain Error Negative Gain Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio (SNDR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation PSR (Power Supply Rejection) PERFORMANCE CURVES Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT Analog Input Ranges Handling Bipolar Input Signals Transfer Functions Digital Inputs REFERENCE CONFIGURATION OPTIONS MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7866 to ADSP-218x AD7866 to TMS320C541 AD7866 to DSP-563xx APPLICATION HINTS Grounding and Layout Evaluating the AD7866 Performance OUTLINE DIMENSIONS Revision History