Datasheet AD7910, AD7920 (Analog Devices)

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250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 AD7910/AD7920 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput rate: 250 kSPS VDD Specified for VDD of 2.35 V to 5.25 V Low power 3.6 mW typ at 250 kSPS with 3 V supplies 10-/12-BIT 12.5 mW typ at 250 kSPS with 5 V supplies VIN T/H SUCCESSIVE APPROXIMATION Wide input bandwidth ADC 71 dB SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays SCLK High speed serial interface CONTROL LOGIC SDATA SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible CS Standby mode: 1 μA max AD7910/AD7920 6-lead SC70 package 8-lead MSOP package GND
02976-001

Figure 1.
APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD7910/AD79201 are, respectively, 10-bit and 12-bit, high 1. 10-/12-bit ADCs in SC70 and MSOP packages. speed, low power, successive approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature 2. Low power consumption. throughput rates up to 250 kSPS. The parts contain a low noise, 3. Flexible power/serial clock speed management. The wide bandwidth track-and-hold amplifier that can handle input conversion rate is determined by the serial clock, allowing frequencies in excess of 13 MHz. the conversion time to be reduced through the serial clock The conversion process and data acquisition are controlled speed increase. This allows the average power consumption using CS and the serial clock, allowing the devices to interface to be reduced when power-down mode is used while not with microprocessors or DSPs. The input signal is sampled on converting. The part also features a power-down mode to the falling edge of CS and the conversion is initiated at this maximize power efficiency at lower throughput rates. Current consumption is 1 μA maximum and 50 nA typically point. There are no pipeline delays associated with the part. when in power-down mode. The AD7910/AD7920 use advanced design techniques to 4. Reference derived from the power supply. achieve very low power dissipation at high throughput rates. 5. No pipeline delay. The parts feature a standard successive The reference for the part is taken internally from VDD. This approximation ADC with accurate control of the sampling allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 to V instant via a CS input and once-off conversion control. DD. The conversion rate is determined by the SCLK. 1 Protected by U.S. Patent No. 6,681,332.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7910 AD7920 TIMING SPECIFICATIONS TIMING EXAMPLES TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7910/AD7920 TO TMS320C541 INTERFACE AD7910/AD7920 TO ADSP-218x AD7910/AD7920 TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE