Datasheet AD7674 (Analog Devices) - 7

AD7674 Data Sheet Table 4. Serial Clock Timings in Master Read After Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns Internal SCLK Period Minimum t19 25 60 120 240 ns Internal SCLK Period Maximum t19 40 80 160 320 ns Internal SCLK High Minimum t20 12 22 50 100 ns Internal SCLK Low Minimum t21 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns BUSY High Width Maximum (Warp Mode) t28 1.75 2.5 4 7 µs BUSY High Width Maximum (Normal Mode) t28 2 2.75 4.25 7.25 µs BUSY High Width Maximum (Impulse Mode) t28 2.25 3 4.5 7.5 µs Rev. B | Page 6 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING Serial Peripheral Interface (SPI) APPLICATIONS INFORMATION LAYOUT EVALUATING AD7674 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES