Datasheet AD7679 (Analog Devices) - 13
| Hersteller | Analog Devices |
| Beschreibung | 18-Bit, 570 kSPS PulSAR A/D Converter |
| Seiten / Seite | 29 / 13 — AD7679. TYPICAL PERFORMANCE CHARACTERISTICS. 2.5. 2.0. 1.5. 1.0. 0.5. -Bi … |
| Revision | A |
| Dateiformat / Größe | PDF / 513 Kb |
| Dokumentensprache | Englisch |
AD7679. TYPICAL PERFORMANCE CHARACTERISTICS. 2.5. 2.0. 1.5. 1.0. 0.5. -Bi 8. B (1. –0.5. INL-LSB (18-Bit). DNL-LS. –1.0. –1.5. –2.0. –2.5. 65536. 131072
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AD7679 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 2.0 1.5 1.5 1.0 t) 1.0 0.5 -Bi 8 0 B (1 0.5 –0.5 INL-LSB (18-Bit) DNL-LS 0 –1.0 –1.5 –0.5 –2.0 –2.5 –1.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE
03085-0-005 03085-0-008 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code
70000 90000 VREF = 5V VREF = 5V 58510 59001 80000 60000 70000 50000 60000 40000 50000 COUNTS 30000 COUNTS 40000 30000 20000 23080 22496 20000 10000 7584 4616 10000 3838 0 0 73 264 0 0 0 2 799 59 0 0 0 1FEBD1FEBE 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 1FEBE 1FEBF 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 CODE IN HEX CODE IN HEX
03085-0-006 03085-0-009 Figure 6. Histogram of 131,072 Conversions of a Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Transition DC Input at the Code Center
100 120 100 80 80 60 60 R OF UNITS R OF UNITS 40 NUMBE NUMBE 40 20 20 0 0 0 0.5 1.0 1.5 2.0 2.5 –2.5 –2.0 –1.5 –1.0 –0.5 0 POSITIVE INL (LSB) NEGATIVE INL (LSB)
03085-0-007 03085-0-010 Figure 7. Typical Positive INL Distribution (424 Units) Figure 10. Typical Negative INL Distribution (424 Units) Rev. A | Page 12 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7679’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
03085-0-005 03085-0-008 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code
70000 90000 VREF = 5V VREF = 5V 58510 59001 80000 60000 70000 50000 60000 40000 50000 COUNTS 30000 COUNTS 40000 30000 20000 23080 22496 20000 10000 7584 4616 10000 3838 0 0 73 264 0 0 0 2 799 59 0 0 0 1FEBD1FEBE 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 1FEBE 1FEBF 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 CODE IN HEX CODE IN HEX
03085-0-006 03085-0-009 Figure 6. Histogram of 131,072 Conversions of a Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Transition DC Input at the Code Center
100 120 100 80 80 60 60 R OF UNITS R OF UNITS 40 NUMBE NUMBE 40 20 20 0 0 0 0.5 1.0 1.5 2.0 2.5 –2.5 –2.0 –1.5 –1.0 –0.5 0 POSITIVE INL (LSB) NEGATIVE INL (LSB)
03085-0-007 03085-0-010 Figure 7. Typical Positive INL Distribution (424 Units) Figure 10. Typical Negative INL Distribution (424 Units) Rev. A | Page 12 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7679’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE