Datasheet AD7940 (Analog Devices)

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3 mW, 100 kSPS, 14-Bit ADC in 6-Lead SOT-23 AD7940 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 100 kSPS VDD Specified for V of 2.5 V to 5.5 V DD Low power 14-BIT SUCCESSIVE 4 mW typ at 100 kSPS with 3 V supplies VIN T/H APPROXIMATION 17 mW typ at 100 kSPS with 5 V supplies ADC Wide input bandwidth: 81 dB SINAD at 10 kHz input frequency SCLK CONTROL Flexible power/serial clock speed management AD7940 SDATA LOGIC No pipeline delays CS High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible GND
03305-0-001
Standby mode: 0.5 µA max
Figure 1.
6-Lead SOT-23 and 8-Lead MSOP packages Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23) APPLICATIONS Type 100 kSPS 250 kSPS 500 kSPS Battery-powered systems
16-Bit True Differential AD7684 AD7687 AD7688
Personal digital assistants
16-Bit Pseudo Differential AD7683 AD7685 AD7686
Medical instruments
16-Bit Unipolar AD7680
Mobile communications
14-Bit True Differential AD7944 AD7947
Instrumentation and control systems Remote data acquisition systems
14-Bit Pseudo Differential AD7942 AD7946 14-Bit Unipolar AD7940
GENERAL DESCRIPTION
This part features a standard successive approximation ADC The AD79401 is a 14-bit, fast, low power, successive with accurate control of the sampling instant via a CS input and approximation ADC. The part operates from a single 2.50 V to once off conversion control. 5.5 V power supply and features throughput rates up to 100 kSPS.
PRODUCT HIGHLIGHTS
The part contains a low noise, wide bandwidth track-and-hold 1. First 14-bit ADC in a SOT-23 package. amplifier that can handle input frequencies in excess of 7 MHz. 2. High throughput with low power consumption. The conversion process and data acquisition are controlled 3. Flexible power/serial clock speed management. The using CS and the serial clock, al owing the devices to interface conversion rate is determined by the serial clock, allowing with microprocessors or DSPs. The input signal is sampled on the conversion time to be reduced through the serial clock the fal ing edge of CS and the conversion is also initiated at this speed increase. This al ows the average power consumption point. There are no pipelined delays associated with the part. to be reduced when a power-down mode is used while not The AD7940 uses advanced design techniques to achieve very converting. The part also features a shutdown mode to low power dissipation at fast throughput rates. The reference for maximize power efficiency at lower throughput rates. the part is taken internally from V Power consumption is 0.5 µA max when in shutdown. DD, which al ows the widest dynamic input range to the ADC. Thus, the analog input range 4. Reference derived from the power supply. for this part is 0 V to V 5. No pipeline delay. DD. The conversion rate is determined by the SCLK frequency. 1Protected by US. Patent No. 6,681,332.
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Document Outline Table of Contents Specifications1F Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Terminology Typical Performance Characteristics Circuit Information Converter Operation Analog Input ADC Transfer Function Typical Connection Diagram Digital Inputs Modes of Operation Normal Mode Power-Down Mode Power vs. Throughput Rate Serial Interface Microprocessor Interfacing AD7940 to TMS320C541 AD7940 to ADSP-218x AD7940 to DSP563xx Application Hints Grounding and Layout Evaluating the AD7940 Performance Outline Dimensions Ordering Guide