Datasheet AD7792, AD7793 (Analog Devices) - 9

HerstellerAnalog Devices
Beschreibung3-Channel, Low Noise, Low Power, 24-Bit Sigma Delta ADC with On-Chip In-Amp and Reference
Seiten / Seite32 / 9 — AD7792/AD7793. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. SCLK 1. 16 …
RevisionB
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DokumentenspracheEnglisch

AD7792/AD7793. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. SCLK 1. 16 DIN. CLK 2. 15 DOUT/RDY. CS 3. 14 DVDD. AD7792/. IOUT1 4. AD7793. AVDD

AD7792/AD7793 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 16 DIN CLK 2 15 DOUT/RDY CS 3 14 DVDD AD7792/ IOUT1 4 AD7793 AVDD

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AD7792/AD7793 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 16 DIN CLK 2 15 DOUT/RDY CS 3 14 DVDD AD7792/ IOUT1 4 13 AD7793 AVDD AIN1(+) TOP VIEW 5 12 GND (Not to Scale) AIN1(–) 6 11 IOUT2 AIN2(+) 7 10 REFIN(–)/AIN3(–)
5 00
AIN2(–) 8 9 REFIN(+)/AIN3(+)
5- 85 04 Figure 5. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. 2 CLK Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed. 3 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 4 IOUT1 Output of Internal Excitation Current Source. The internal excitation current source can be made available at this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. 5 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−). 6 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−). 7 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−). 8 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−). 9 REFIN(+)/AIN3(+) Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage REFIN(+) − REFIN(−) is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Alternatively, this pin can function as AIN3(+) where AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(−). 10 REFIN(−)/AIN3(−) Negative Reference Input/Analog Input. REFIN(−) is the negative reference input for REFIN. This reference input can lie anywhere between GND and AVDD − 0.1 V. This pin also functions as AIN3(−), which is the negative terminal of the differential analog input pair AIN3(+)/AIN3(−). 11 IOUT2 Output of Internal Excitation Current Source. The internal excitation current source can be made available at this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. 12 GND Ground Reference Point. 13 AVDD Supply Voltage, 2.7 V to 5.25 V. 14 DVDD Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is between 2.7 V and 5.25 V. The DVDD voltage is independent of the voltage on AVDD; therefore, AVDD can equal 5 V with DVDD at 3 V or vice versa. Rev. B | Page 9 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTPUT NOISE AND RESOLUTION SPECIFICATIONS EXTERNAL REFERENCE INTERNAL REFERENCE TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATIONS REGISTER RS2, RS1, RS0 = 0, 0, 0 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7792)/0x88 (AD7793) MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 DATA REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00) ID REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXA (AD7792)/0xXB (AD7793) IO REGISTER RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 OFFSET REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7792)/0x800000 (AD7793) FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7792)/0x5XXX00 (AD7793) ADC CIRCUIT INFORMATION OVERVIEW DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL INSTRUMENTATION AMPLIFIER BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS EXCITATION CURRENTS BIAS VOLTAGE GENERATOR REFERENCE RESET AVDD MONITOR CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD OUTLINE DIMENSIONS ORDERING GUIDE