Datasheet AD7792, AD7793 (Analog Devices) - 5

HerstellerAnalog Devices
Beschreibung3-Channel, Low Noise, Low Power, 24-Bit Sigma Delta ADC with On-Chip In-Amp and Reference
Seiten / Seite32 / 5 — AD7792/AD7793. Parameter. AD7792B/AD7793B1. Unit. Test Conditions/Comments
RevisionB
Dateiformat / GrößePDF / 464 Kb
DokumentenspracheEnglisch

AD7792/AD7793. Parameter. AD7792B/AD7793B1. Unit. Test Conditions/Comments

AD7792/AD7793 Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments

Modelllinie für dieses Datenblatt

Textversion des Dokuments

link to page 3 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5
AD7792/AD7793 Parameter AD7792B/AD7793B1 Unit Test Conditions/Comments
SCLK, CLK, and DIN (Schmitt- Triggered Input)2 VT(+) 1.4/2 V min/V max DVDD = 5 V VT(–) 0.8/1.7 V min/V max DVDD = 5 V VT(+) − VT(−) 0.1/0.17 V min/V max DVDD = 5 V VT(+) 0.9/2 V min/V max DVDD = 3 V VT(–) 0.4/1.35 V min/V max DVDD = 3 V VT(+) − VT(−) 0.06/0.13 V min/V max DVDD = 3 V Input Currents ±10 μA max VIN = DVDD or GND Input Capacitance 10 pF typ All digital inputs LOGIC OUTPUTS (INCLUDING CLK) VOH, Output High Voltage2 DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 μA VOL, Output Low Voltage2 0.4 V max DVDD = 3 V, ISINK = 100 μA VOH, Output High Voltage2 4 V min DVDD = 5 V, ISOURCE = 200 μA VOL, Output Low Voltage2 0.4 V max DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY)/800 μA (CLK) Floating-State Leakage Current ±10 μA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset binary SYSTEM CALIBRATION2 Full-Scale Calibration Limit +1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS7 Power Supply Voltage AVDD to GND 2.7/5.25 V min/max DVDD to GND 2.7/5.25 V min/max Power Supply Currents IDD Current 140 μA max 110 μA typ @ AVDD = 3 V, 125 μA typ @ AVDD = 5 V, unbuffered mode, external reference 185 μA max 130 μA typ @ AVDD = 3 V, 165 μA typ @ AVDD = 5 V, buffered mode, gain = 1 or 2, external reference 400 μA max 300 μA typ @ AVDD = 3 V, 350 μA typ @ AVDD = 5 V, gain = 4 to 128, external reference 500 μA max 400 μA typ @ AVDD = 3 V, 450 μA typ @ AVDD = 5 V, gain = 4 to 128, internal reference IDD (Power-Down Mode) 1 μA max 1 Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AVDD − 16 V typically. When this voltage is exceeded, the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AVDD − 1.6 V. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected. 4 Recalibration at any temperature removes these errors. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled. Rev. B | Page 5 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTPUT NOISE AND RESOLUTION SPECIFICATIONS EXTERNAL REFERENCE INTERNAL REFERENCE TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATIONS REGISTER RS2, RS1, RS0 = 0, 0, 0 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7792)/0x88 (AD7793) MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 DATA REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00) ID REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXA (AD7792)/0xXB (AD7793) IO REGISTER RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 OFFSET REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7792)/0x800000 (AD7793) FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7792)/0x5XXX00 (AD7793) ADC CIRCUIT INFORMATION OVERVIEW DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL INSTRUMENTATION AMPLIFIER BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS EXCITATION CURRENTS BIAS VOLTAGE GENERATOR REFERENCE RESET AVDD MONITOR CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD OUTLINE DIMENSIONS ORDERING GUIDE