Datasheet AD9219 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| Seiten / Seite | 57 / 3 — AD9219. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 12/11—Rev. D to … |
| Revision | F |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
AD9219. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 12/11—Rev. D to Rev. E. 5/07—Rev. 0 to Rev. A. 5/10—Rev. C to Rev. D
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AD9219 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Input Considerations ... 20 Applications ... 1 Clock Input Considerations .. 23 General Description ... 1 Serial Port Interface (SPI) .. 31 Functional Block Diagram .. 1 Hardware Interface ... 31 Product Highlights ... 1 Memory Map .. 33 Revision History ... 2 Reading the Memory Map Table .. 33 Specifications ... 4 Reserved Locations .. 33 AC Specifications .. 5 Default Values ... 33 Digital Specifications ... 6 Logic Levels ... 33 Switching Specifications .. 7 Evaluation Board .. 37 Timing Diagrams .. 8 Power Supplies .. 37 Absolute Maximum Ratings .. 10 Input Signals.. 37 Thermal Impedance ... 10 Output Signals .. 37 ESD Caution .. 10 Default Operation and Jumper Selection Settings ... 38 Pin Configuration and Function Descriptions ... 11 Alternative Analog Input Drive Configuration.. 39 Equivalent Circuits ... 13 Outline Dimensions ... 53 Typical Performance Characteristics ... 15 Ordering Guide .. 53 Theory of Operation .. 20
REVISION HISTORY 12/11—Rev. D to Rev. E 5/07—Rev. 0 to Rev. A
Added Exposed Pad Notation to Figure 5 ... 11 Changes to Features .. 1 Changes to Output Signals Section and Figure 71 ... 37 Changes to Logic Output (SDIO/ODM) Section .. 5 Change to Default Operation and Jumper Selection Settings Added Endnote 3 to Table 3 ... 5 Section .. 38 Changes to Pipeline Latency .. 6 Change to Figure 74 ... 41 Changes to Figure 2 to Figure 4 ... 7 Changed LFCSP_WQ to LFCSP_VQ Throughout .. 53 Changes to Figure 10 .. 12 Added Endnote 2 in Ordering Guide .. 53 Changes to Figure 15, Figure 23 to Figure 26 Captions .. 14
Changes to Figure 16, Figure 37, Figure 39, and Figure 40... 14
5/10—Rev. C to Rev. D
Added Figure 46 and Figure 47 .. 20 Updated Outline Dimensions ... 52 Change to Figure 50 ... 21 Changes to Ordering Guide .. 52 Changes to Figure 51 .. 21 Changes to Clock Duty Cycle Considerations Section ... 22
4/10—Rev. B to Rev. C
Changes to Power Dissipation and Changes to Table 16 .. 33 Power-Down Mode Section .. 23 Updated Outline Dimensions ... 52 Changes to Figure 58 .. 23 Changes to Figure 61 to Figure 63 Captions ... 25
7/07—Rev. A to Rev. B
Change to Table 8 ... 25 Changes to Figure 2 and Figure 4 ... 7 Changes to Digital Outputs and Timing Section ... 26 Changes to Table 17 .. 50 Changes to Table 9 Endnote .. 26 Added Table 10 ... 27 Deleted Figure 62 and Figure 63 .. 27 Rev. E | Page 2 of 56 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
AD9219 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Input Considerations ... 20 Applications ... 1 Clock Input Considerations .. 23 General Description ... 1 Serial Port Interface (SPI) .. 31 Functional Block Diagram .. 1 Hardware Interface ... 31 Product Highlights ... 1 Memory Map .. 33 Revision History ... 2 Reading the Memory Map Table .. 33 Specifications ... 4 Reserved Locations .. 33 AC Specifications .. 5 Default Values ... 33 Digital Specifications ... 6 Logic Levels ... 33 Switching Specifications .. 7 Evaluation Board .. 37 Timing Diagrams .. 8 Power Supplies .. 37 Absolute Maximum Ratings .. 10 Input Signals.. 37 Thermal Impedance ... 10 Output Signals .. 37 ESD Caution .. 10 Default Operation and Jumper Selection Settings ... 38 Pin Configuration and Function Descriptions ... 11 Alternative Analog Input Drive Configuration.. 39 Equivalent Circuits ... 13 Outline Dimensions ... 53 Typical Performance Characteristics ... 15 Ordering Guide .. 53 Theory of Operation .. 20
REVISION HISTORY 12/11—Rev. D to Rev. E 5/07—Rev. 0 to Rev. A
Added Exposed Pad Notation to Figure 5 ... 11 Changes to Features .. 1 Changes to Output Signals Section and Figure 71 ... 37 Changes to Logic Output (SDIO/ODM) Section .. 5 Change to Default Operation and Jumper Selection Settings Added Endnote 3 to Table 3 ... 5 Section .. 38 Changes to Pipeline Latency .. 6 Change to Figure 74 ... 41 Changes to Figure 2 to Figure 4 ... 7 Changed LFCSP_WQ to LFCSP_VQ Throughout .. 53 Changes to Figure 10 .. 12 Added Endnote 2 in Ordering Guide .. 53 Changes to Figure 15, Figure 23 to Figure 26 Captions .. 14
Changes to Figure 16, Figure 37, Figure 39, and Figure 40... 14
5/10—Rev. C to Rev. D
Added Figure 46 and Figure 47 .. 20 Updated Outline Dimensions ... 52 Change to Figure 50 ... 21 Changes to Ordering Guide .. 52 Changes to Figure 51 .. 21 Changes to Clock Duty Cycle Considerations Section ... 22
4/10—Rev. B to Rev. C
Changes to Power Dissipation and Changes to Table 16 .. 33 Power-Down Mode Section .. 23 Updated Outline Dimensions ... 52 Changes to Figure 58 .. 23 Changes to Figure 61 to Figure 63 Captions ... 25
7/07—Rev. A to Rev. B
Change to Table 8 ... 25 Changes to Figure 2 and Figure 4 ... 7 Changes to Digital Outputs and Timing Section ... 26 Changes to Table 17 .. 50 Changes to Table 9 Endnote .. 26 Added Table 10 ... 27 Deleted Figure 62 and Figure 63 .. 27 Rev. E | Page 2 of 56 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide