Datasheet AD9233 (Analog Devices) - 24

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AD9233 SERIAL PORT INTERFACE (SPI)
The AD9233 SPI allows the user to configure the converter for In addition to word length, the instruction phase determines if specific functions or operations through a structured register the serial frame is a read or write operation, allowing the serial space provided inside the ADC. This provides the user added port to be used to both program the chip as well as read the flexibility and customization depending on the application. contents of the on-chip memory. If the instruction is a readback Addresses are accessed via the serial port and can be written to operation, performing a readback causes the serial data input/ or read from via the port. Memory is organized into bytes that output (SDIO) pin to change direction from an input to an are further divided into fields, as documented in the Memory output at the appropriate point in the serial frame. Map section. For detailed operational information, see the Interfacing to High Speed ADCs via SPI User Manual. Data can be sent in MSB first or in LSB first mode. MSB first is the default on power up and can be changed via the
CONFIGURATION USING THE SPI
configuration register. For more information, see the Interfacing As summarized in Table 13, three pins define the SPI of this to High Speed ADCs via SPI User Manual. ADC. The SCLK/DFS pin synchronizes the read and write data presented to the ADC. The SDIO/DCS dual-purpose pin allows
Table 14. SPI Timing Diagram Specifications
data to be sent and read from the internal ADC memory map
Name Description
registers. The CSB pin is an active low control that enables or tDS Setup time between data and rising edge of SCLK disables the read and write cycles. tDH Hold time between data and rising edge of SCLK t CLK Period of the clock
Table 13. Serial Port Interface Pins
tS Setup time between CSB and SCLK
Mnemonic Description
tH Hold time between CSB and SCLK SCLK/DFS SCLK (Serial Clock) is the serial shift clock in. SCLK tHI Minimum period that SCLK should be in a logic high state synchronizes serial interface reads and writes. tLO Minimum period that SCLK should be in a logic low state SDIO/DCS SDIO (Serial Data Input/Output) is a dual-purpose pin. The typical role for this pin is an input and
HARDWARE INTERFACE
output depending on the instruction being sent and the relative position in the timing frame. The pins described in Table 13 comprise the physical interface CSB CSB (Chip Select Bar) is an active low control that between the user’s programming device and the serial port of gates the read and write cycles. the AD9233. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning The falling edge of the CSB in conjunction with the rising edge as an input during write phases and as an output during readback. of the SCLK determines the start of the framing. Figure 57 and The SPI interface is flexible enough to be controlled by either Table 14 provide an example of the serial timing and its PROM or PIC microcontrollers. This provides the user with the definitions. ability to use an alternate method to program the ADC. One Other modes involving the CSB are available. The CSB can be method is described in detail in the Application Note AN-812. held low indefinitely, permanently enabling the device (this is When the SPI interface is not used, some pins serve a dual called streaming). The CSB can stall high between bytes to function. When strapped to AVDD or ground during device allow for additional external timing. When CSB is tied high power on, the pins are associated with a specific function. during power up, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. If
CONFIGURATION WITHOUT THE SPI
CSB is high at power up and then brought low to activate the In applications that do not interface to the SPI control registers, SPI, the SPI pin secondary functions are no longer available, the SDIO/DCS and SCLK/DFS pins serve as standalone CMOS- unless the device power is cycled. compatible control pins. When the device is powered up with During an instruction phase, a 16-bit instruction is transmitted. the CSB chip select connected to AVDD, the serial port interface is Data follows the instruction phase and the length is determined disabled. In this mode, it is assumed that the user intends to use by the W0 bit and the W1 bit. All data is composed of 8-bit the pins as static control lines for the output data format and words. The first bit of each individual byte of serial data indicates duty cycle stabilizer (see Table 10). For more information, see whether a read or write command is issued. This allows the the Interfacing to High Speed ADCs via SPI User Manual. serial data input/output (SDIO) pin to change direction from an input to an output. Rev. A | Page 23 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Clock Duty Cycle JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE Power-Down Mode Standby Mode DIGITAL OUTPUTS Out-of-Range (OR) Condition Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels SPI-Accessible Features LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN VREF RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE