Datasheet AD9461 (Analog Devices) - 29
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 130 MSPS A/D Converter |
| Seiten / Seite | 29 / 29 — AD9461. OUTLINE DIMENSIONS. 1.20. 16.00 BSC SQ. 0.75 0.60. MAX. 14.00 BSC … |
| Dateiformat / Größe | PDF / 714 Kb |
| Dokumentensprache | Englisch |
AD9461. OUTLINE DIMENSIONS. 1.20. 16.00 BSC SQ. 0.75 0.60. MAX. 14.00 BSC SQ. 0.45. 100. PIN 1. TOP VIEW. EXPOSED. 9.50 SQ. (PINS DOWN). PAD. 1.05
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 29
AD9461 OUTLINE DIMENSIONS 1.20 16.00 BSC SQ 0.75 0.60 MAX 14.00 BSC SQ 0.45 100 76 76 100 1 75 75 1 PIN 1 TOP VIEW EXPOSED 9.50 SQ (PINS DOWN) PAD 1.05 0° MIN 0.20 BOTTOM VIEW 1.00 0.09 (PINS UP) 25 51 51 25 0.95 7° 26 50 50 26 3.5° VIEW A 0.50 BSC 0.15 0.27 SEATING 0° LEAD PITCH 0.05 PLANE 0.08 MAX 0.22 COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL -A TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE 06 05 SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE 04 DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 39. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters
ORDERING GUIDE Model Temperature Range Package Description Package Option
AD9461BSVZ1 –40°C to +85°C 100-Lead TQFP_EP SV-100-3 AD9461-LVDS/PCB AD9461-100 LVDS Mode Evaluation Board 1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06011–0–4/06(0)
Rev. 0 | Page 28 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9461 OUTLINE DIMENSIONS 1.20 16.00 BSC SQ 0.75 0.60 MAX 14.00 BSC SQ 0.45 100 76 76 100 1 75 75 1 PIN 1 TOP VIEW EXPOSED 9.50 SQ (PINS DOWN) PAD 1.05 0° MIN 0.20 BOTTOM VIEW 1.00 0.09 (PINS UP) 25 51 51 25 0.95 7° 26 50 50 26 3.5° VIEW A 0.50 BSC 0.15 0.27 SEATING 0° LEAD PITCH 0.05 PLANE 0.08 MAX 0.22 COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL -A TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE 06 05 SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE 04 DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 39. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters
ORDERING GUIDE Model Temperature Range Package Description Package Option
AD9461BSVZ1 –40°C to +85°C 100-Lead TQFP_EP SV-100-3 AD9461-LVDS/PCB AD9461-100 LVDS Mode Evaluation Board 1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06011–0–4/06(0)
Rev. 0 | Page 28 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE