Datasheet AD7264 (Analog Devices) - 10

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Data Sheet AD7264 Pin No. Mnemonic Description
48, 47, 46, 45 CA+, CA−, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A CB+, CB− and Comparator B. These two comparators have very low power consumption. 13, 14, 15, 16 CC+, CC−, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C CD+, CD− and Comparator D. These two comparators offer very fast propagation delays. 5, 6, 8, 19, 42 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7264. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and CC_CD_ GND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. CA_CB_GND and CC_CD_GND can be tied to AGND. 28 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7264. The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 30, 29, 26, 25 COUTA, COUTB, Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective COUTC, COUTD comparator. These are digital output pins with logic levels determined by the VDRIVE supply. 32, 31 DOUTA, DOUTB Serial Data Outputs. The data output from the AD7264 is supplied to each pin as a serial data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of 33 SCLK cycles are required to perform the conversion and access the 14-bit data. During the conversion process, the data output pins are in three-state and, when the conversion is completed, the 19th SCLK edge clocks out the MSB. The data appears simultaneously on both pins from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for a further 14 SCLK cycles on either DOUTA or DOUTB following the initial 33 SCLK cycles, the data from the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. 40, 39, 38, 37 G0, G1, G2, G3 Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four pins are tied low, the PD0/DIN pin acts as a data input pin, DIN, and all programming is made via the control register. See Table 6. 27 VDRIVE Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what voltage the interface operates, including the comparator outputs. This pin should be decoupled to DGND. 44, 17 CA_CB_GND, Comparator Ground. Ground reference point for all comparator circuitry on the AD7264. Both the CC_CD_GND CA_CB_GND and CC_CD_GND pins should connect to the GND plane of a system and can be tied to AGND. The DGND, AGND, CA_CB_GND, and CC_CD_GND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 24 REFSEL Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7264 through the VREFA and/or VREFB pins. Rev. D | Page 9 of 29 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTER SYSTEM GAIN CALIBRATION APPLICATIONS INFORMATION GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE