Datasheet AD9267 (Analog Devices) - 4
| Hersteller | Analog Devices |
| Beschreibung | 10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator |
| Seiten / Seite | 25 / 4 — AD9267. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Parameter Temp. Min. … |
| Dateiformat / Größe | PDF / 562 Kb |
| Dokumentensprache | Englisch |
AD9267. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Parameter Temp. Min. Typ. Max. Unit
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4
AD9267 SPECIFICATIONS DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN1 = −2.0 dBFS, unless otherwise noted.
Table 1. Parameter Temp Min Typ Max Unit
RESOLUTION Full 16 Bits ANALOG INPUT BANDWIDTH 10 MHz ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.025 ±0.2 % FSR Gain Error Full ±0.7 ±2.5 % FSR Integral Nonlinearity (INL)2 25°C ±1.5 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.035 ±0.2 % FSR Gain Error Full ±0.2 ±1.2 % FSR TEMPERATURE DRIFT Offset Error Full ±1.5 ppm/°C Gain Error Full ±47 ppm/°C INTERNAL VOLTAGE REFERENCE Full 496 500 505 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 V p-p diff Input Resistance Full 1 kΩ Input Common Mode Full 1.7 1.8 1.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current I 2 AVDD , PLL Enabled Full 150.7 162 mA I 2 AVDD , PLL Disabled Full 151.2 161 mA I 2 CVDD , PLL Enabled Full 57 63 mA I 2 CVDD , PLL Disabled Full 8 9.2 mA I 2 DVDD Full 71.5 78 mA I 2 DRVDD Full 0.26 0.3 mA POWER CONSUMPTION Sine Wave Input2, PLL Disabled Full 416 mW Sine Wave Input, PLL Enabled Full 503 mW Power-Down Power 25°C 110 mW Standby Power 25°C 9 mW Sleep Power Full 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave with approximately 5 pF loading on each output bit. Rev. 0 | Page 3 of 24 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Power Dissipation and Standby Mode Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
AD9267 SPECIFICATIONS DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN1 = −2.0 dBFS, unless otherwise noted.
Table 1. Parameter Temp Min Typ Max Unit
RESOLUTION Full 16 Bits ANALOG INPUT BANDWIDTH 10 MHz ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.025 ±0.2 % FSR Gain Error Full ±0.7 ±2.5 % FSR Integral Nonlinearity (INL)2 25°C ±1.5 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.035 ±0.2 % FSR Gain Error Full ±0.2 ±1.2 % FSR TEMPERATURE DRIFT Offset Error Full ±1.5 ppm/°C Gain Error Full ±47 ppm/°C INTERNAL VOLTAGE REFERENCE Full 496 500 505 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 V p-p diff Input Resistance Full 1 kΩ Input Common Mode Full 1.7 1.8 1.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current I 2 AVDD , PLL Enabled Full 150.7 162 mA I 2 AVDD , PLL Disabled Full 151.2 161 mA I 2 CVDD , PLL Enabled Full 57 63 mA I 2 CVDD , PLL Disabled Full 8 9.2 mA I 2 DVDD Full 71.5 78 mA I 2 DRVDD Full 0.26 0.3 mA POWER CONSUMPTION Sine Wave Input2, PLL Disabled Full 416 mW Sine Wave Input, PLL Enabled Full 503 mW Power-Down Power 25°C 110 mW Standby Power 25°C 9 mW Sleep Power Full 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave with approximately 5 pF loading on each output bit. Rev. 0 | Page 3 of 24 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Power Dissipation and Standby Mode Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide