Datasheet AD9269 (Analog Devices) - 9

AD9269 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 4. AD9269-20/AD9269-40 AD9269-65 AD9269-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Ma Unit x
CLOCK INPUT PARAMETERS Input Clock Rate Full 480 480 480 MHz Conversion Rate1 Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 50/25 15.38 12.5 ns CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (tDCO) Full 3 3 3 ns DCO to Data Skew (tSKEW) Full 0.1 0.1 0.1 ns Pipeline Delay (Latency) Full 9 9 9 Cycles With QEC Active Full 11 11 11 Cycles Wake-Up Time2 Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors.
N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A/CH B DATA N – 9 N – 8 N – 7 N – 6 N – 5
002 8-
tPD
853 0 Figure 2. CMOS Output Data Timing
N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A/CH B DATA CH A CH B CH A CH B CH A CH B CH A CH B CH A AS APPEARS ON N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 CHA OUTPUT PINS
003
t
38-
PD
085 Figure 3. CMOS Interleaved Output Timing, Output as Appears on Channel A Output Pins Rev. A | Page 8 of 40 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9269-80 AD9269-65 AD9269-40 AD9269-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB (Pin 47) Bits [6:4]—Open Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 1—Open Bit 0—Disable SDIO Pull-Down QEC Control 0 (Register 0x110) Bits[7:6]—Open Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain Bits[2:0]—DC Enable/Phase Enable/Gain Enable QEC Control 1 (Register 0x111) Bits[7:3]—Open Bit 2—Force DC Bit 1—Force Phase Bit 0—Force Gain QEC Gain Bandwidth Control (Register 0x112) Bits[7:5]—Open Bits[4:0]—KEXP_GAIN QEC Phase Bandwidth Control (Register 0x113) Bits[7:5]—Open Bits[4:0]—KEXP_PHASE QEC DC Bandwidth Control (Register 0x114) Bits[7:5]—Open Bits[4:0]—KEXP_DC QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and Register 0x117) Bits[14:0]—Initial Gain QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and Register 0x119) Bits[12:0]—Initial Phase QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and Register 0x11B) Bits[13:0]—Initial DC I QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and Register 0x11D) Bits[13:0]—Initial DC Q Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide