Datasheet AD9650 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| Seiten / Seite | 45 / 3 — AD9650. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 12/14—Rev. A to … |
| Revision | A |
| Dateiformat / Größe | PDF / 1.5 Mb |
| Dokumentensprache | Englisch |
AD9650. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 12/14—Rev. A to Rev. B. 11/11—Rev. 0 to Rev. A
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AD9650 Data Sheet TABLE OF CONTENTS
Features .. 1 ADC Architecture .. 29 Applications ... 1 Analog Input Considerations ... 29 General Description ... 1 Voltage Reference ... 32 Functional Block Diagram .. 1 Channel/Chip Synchronization .. 34 Product Highlights ... 1 Power Dissipation and Standby Mode .. 34 Revision History ... 2 Digital Outputs ... 35 Specifications ... 3 Timing.. 35 ADC DC Specifications ... 3 Built-In Self-Test (BIST) and Output Test .. 36 ADC AC Specifications ... 4 Built-In Self-Test (BIST) .. 36 Digital Specifications ... 5 Output Test Modes ... 36 Switching Specifications .. 7 Serial Port Interface (SPI) .. 37 Timing Specifications .. 8 Configuration Using the SPI ... 37 Absolute Maximum Ratings .. 10 Hardware Interface ... 38 Thermal Characteristics .. 10 Configuration Without the SPI .. 38 ESD Caution .. 10 SPI Accessible Features .. 38 Pin Configurations and Function Descriptions ... 11 Memory Map .. 39 Typical Performance Characteristics ... 15 Reading the Memory Map Register Table ... 39 AD9650-25 .. 15 Memory Map Register Table ... 40 AD9650-65 .. 18 Memory Map Register Descriptions .. 42 AD9650-80 .. 21 Applications Information .. 43 AD9650-105 .. 24 Design Guidelines .. 43 Equivalent Circuits ... 28 Outline Dimensions ... 44 Theory of Operation .. 29 Ordering Guide .. 44
REVISION HISTORY 12/14—Rev. A to Rev. B
Changes to Figure 83 ... 32 Changes to Table 16 .. 38 Deleted Register 0x10; Table 17 .. 41 Updated Outline Dimensions ... 44
11/11—Rev. 0 to Rev. A
Changes to Table 17 .. 40
7/10—Revision 0: Initial Version
Rev. B | Page 2 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9650-25 AD9650-65 AD9650-80 AD9650-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Large-Signal FFT Small-Signal FFT Static Linearity Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only Bit 1—Clock Divider SYNC Enable Bit 0—Master SYNC Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
AD9650 Data Sheet TABLE OF CONTENTS
Features .. 1 ADC Architecture .. 29 Applications ... 1 Analog Input Considerations ... 29 General Description ... 1 Voltage Reference ... 32 Functional Block Diagram .. 1 Channel/Chip Synchronization .. 34 Product Highlights ... 1 Power Dissipation and Standby Mode .. 34 Revision History ... 2 Digital Outputs ... 35 Specifications ... 3 Timing.. 35 ADC DC Specifications ... 3 Built-In Self-Test (BIST) and Output Test .. 36 ADC AC Specifications ... 4 Built-In Self-Test (BIST) .. 36 Digital Specifications ... 5 Output Test Modes ... 36 Switching Specifications .. 7 Serial Port Interface (SPI) .. 37 Timing Specifications .. 8 Configuration Using the SPI ... 37 Absolute Maximum Ratings .. 10 Hardware Interface ... 38 Thermal Characteristics .. 10 Configuration Without the SPI .. 38 ESD Caution .. 10 SPI Accessible Features .. 38 Pin Configurations and Function Descriptions ... 11 Memory Map .. 39 Typical Performance Characteristics ... 15 Reading the Memory Map Register Table ... 39 AD9650-25 .. 15 Memory Map Register Table ... 40 AD9650-65 .. 18 Memory Map Register Descriptions .. 42 AD9650-80 .. 21 Applications Information .. 43 AD9650-105 .. 24 Design Guidelines .. 43 Equivalent Circuits ... 28 Outline Dimensions ... 44 Theory of Operation .. 29 Ordering Guide .. 44
REVISION HISTORY 12/14—Rev. A to Rev. B
Changes to Figure 83 ... 32 Changes to Table 16 .. 38 Deleted Register 0x10; Table 17 .. 41 Updated Outline Dimensions ... 44
11/11—Rev. 0 to Rev. A
Changes to Table 17 .. 40
7/10—Revision 0: Initial Version
Rev. B | Page 2 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9650-25 AD9650-65 AD9650-80 AD9650-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Large-Signal FFT Small-Signal FFT Static Linearity Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only Bit 1—Clock Divider SYNC Enable Bit 0—Master SYNC Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE