16-Bit, 200 MSPS/250 MSPSAnalog-to-Digital ConverterData SheetAD9467FEATURESFUNCTIONAL BLOCK DIAGRAM75.5 dBFS SNR to 210 MHz at 250 MSPSAVDD1AVDD2AVDD3SPIVDDDRVDD(1.8V)(3.3V)(1.8V)(1.8V TO 3.3V)(1.8V)90 dBFS SFDR to 300 MHz at 250 MSPSCSBSFDR at 170 MHz at 250 MSPSAD9467SDIO92 dBFS at −1 dBFSBUFFERSCLK100 dBFS at −2 dBFSVIN+16PIPELINE260 fs rms jitterVIN–ADCLVDSOR+/OR–OUTPUTD15+/D15–Excellent linearity at 250 MSPS16STAGINGTODNL = ±0.5 LSB typicalD0+/D0–CLK+CLOCK2INL = ±3.5 LSB typicalAND TIMINGDCO+/DCO–CLK–MANAGEMENTREF2 V p-p to 2.5 V p-p (default) differential full-scaleinput (programmable) 001 Integrated input bufferAGNDXVREFDRGND 09029- External reference support option Figure 1. Clock duty cycle stabilizerOutput clock availableSerial port controlBuilt-in selectable digital test pattern generationSelectable output data formatLVDS outputs (ANSI-644 compatible)1.8 V and 3.3 V supply operationAPPLICATIONS A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. Multicarrier, multimode cellular receivers The internal power-down feature supported via the SPI typically Antenna array positioning consumes less than 5 mW when disabled. Power amplifier linearization Broadband wireless Optional features allow users to implement various selectable Radar operating conditions, including input range, data format select, Infrared imaging and output data test patterns. Communications instrumentation The AD9467 is available in a Pb-free, 72-lead, LFCSP specified