Datasheet AD7608 (Analog Devices) - 8

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Data Sheet AD7608 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description
t13 Delay from CSE until DB[15:0] three-state disabled A A 16 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V t 3 14 Data access time after RDE falling edge A A 16 ns VDRIVE above 4.75 V 21 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 32 ns VDRIVE above 2.3 V t15 6 ns Data hold time after RDE falling edge A A t16 6 ns CSE to DB[15:0] hold time A A t17 22 ns Delay from CSE rising edge to DB[15:0] three-state enabled A A SERIAL READ OPERATION fSCLK Frequency of serial read clock 23.5 MHz VDRIVE above 4.75 V 17 MHz VDRIVE above 3.3 V 14.5 MHz VDRIVE above 2.7 V 11.5 MHz VDRIVE above 2.3 V t18 Delay from CSE until DOUTA/DOUTB three-state disabled/delay from CSE until A A A A MSB valid 15 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 30 ns VDRIVE = 2.3 V to 2.7 V t 3 19 Data access time after SCLK rising edge 1F 17 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 27 ns VDRIVE above 2.7 V 34 ns VDRIVE above 2.3 V t20 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK ns SCLK high pulse width t22 7 SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 ns CSE rising edge to DOUTA/DOUTB three-state enabled A A FRSTDATA OPERATION t24 Delay from CSE falling edge until FRSTDATA three-state disabled A A 15 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V t25 ns Delay from CSE falling edge until FRSTDATA high, serial mode A A 15 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V t26 Delay from RDE falling edge to FRSTDATA high A A 16 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V Rev. A | Page 7 of 32 Document Outline Features Applications Companion Products Functional Block Diagram Table of Contents Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference External Reference Mode Internal Reference Mode Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (/SER SEL = 0) Serial Interface (/SER SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide