Datasheet AD9643 (Analog Devices) - 3

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Data Sheet AD9643 SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, unless otherwise noted.
Table 1. AD9643- 170 AD9643- 210 AD9643- 250 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±10 ±10 ±10 mV Gain Error Full +2/−6 +3/−5 ±4 %FSR Differential Nonlinearity (DNL) Full ±0.75 ±0.75 ±0.75 LSB 25°C ±0.25 ±0.25 ±0.25 LSB Integral Nonlinearity (INL)1 Full ±1.8 ±2 ±3.5 LSB 25°C ±1.5 ±1.5 ±1.5 LSB MATCHING CHARACTERISTIC Offset Error Full ±13 ±13 ±13 mV Gain Error Full ±2.5/ −2/ −2.5/ %FSR +3.5 +3.5 +3.5 TEMPERATURE DRIFT Offset Error Full ±5 ±5 ±5 ppm/°C Gain Error Full ±70 ±80 ±100 ppm/°C INPUT REFERRED NOISE VREF = 1.75 V 25°C 1.33 1.33 1.33 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 2.5 pF Input Resistance3 Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current I 1 AVDD Full 196 250 217 265 256 275 mA I 1 DRVDD Full 145 160 160 185 180 210 mA POWER CONSUMPTION Sine Wave Input (DRVDD = 1.8 V) Full 614 680 785 mW Standby Power4 Full 90 90 90 mW Power-Down Power Full 10 10 10 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND). Rev. E | Page 3 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange (OR) Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Description Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port Outline Dimensions Ordering Guide