Datasheet AD9653 (Analog Devices) - 32

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Data Sheet AD9653 SERIAL PORT INTERFACE (SPI)
The AD9653 serial port interface (SPI) allows the user to configure The falling edge of the CSB, in conjunction with the rising edge the converter for specific functions or operations through a of the SCLK, determines the start of the framing. An example of structured register space provided inside the ADC. The SPI the serial timing and its definitions can be found in Figure 75 offers the user added flexibility and customization, depending on and Table 7. the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. The CSB can be can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. This mode turns High Speed ADCs via SPI. on any SPI pin secondary functions.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK pin, the SDIO Data follows the instruction phase, and its length is determined pin, and the CSB pin (see Table 17). The SCLK (a serial clock) is by the W0 and W1 bits. used to synchronize the read and write data presented from and In addition to word length, the instruction phase determines to the ADC. The SDIO (serial data input/output) is a dual- whether the serial frame is a read or write operation, allowing purpose pin that allows data to be sent to and read from the the serial port to be used both to program the chip and to read internal ADC memory map registers. The CSB (chip select bar) the contents of the on-chip memory. The first bit of the first byte in is an active low control that enables or disables the read and a multibyte serial data transfer frame indicates whether a read write cycles. command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial
Table 17. Serial Port Interface Pins
data input/output (SDIO) pin to change direction from an input to
Pin Function
an output at the appropriate point in the serial frame. SCLK Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. All data is composed of 8-bit words. Data can be sent in MSB- SDIO Serial data input/output. A dual-purpose pin that first mode or in LSB-first mode. MSB-first mode is the default typically serves as an input or an output, depending on on power-up and can be changed via the SPI port configuration the instruction being sent and the relative position in the register. For more information about this and other features, timing frame. see the AN-877 Application Note, Interfacing to High Speed CSB Chip select bar. An active low control that gates the read ADCs via SPI. and write cycles.
t t HIGH DS tCLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE
073
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
10538- Figure 75. Serial Port Interface Timing Diagram Rev. E | Page 31 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE