Datasheet AD9635 (Analog Devices) - 18

Data Sheet AD9635 0.25 110 SFDR 100 0.20 90 0.15 80 SNRFS Bc) 0.10 /d 70 S B) S BF 60 L d ( 0.05 50 DR ( DNL F 0 S 40 NR/ S 30 –0.05 20 –0.10 10 –0.15 0 1 10 30 50 70 90 110 130
074
343 685 1027 1369 1711 2053 2395 2737 3079 3421 3763 4105
073
SAMPLE RATE (MSPS)
10577-
OUTPUT CODE
10577- Figure 38. DNL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS Figure 41. SNR/SFDR vs. Sample Rate; fIN = 9.7 MHz, fSAMPLE = 125 MSPS
2,500,000 110 0.42LSB rms 100 SFDR 2,000,000 90 80 S Bc) T /d 70 1,500,000 HI S SNRFS F BF 60 d R O 50 BE DR ( 1,000,000 F S 40 NUM NR/ S 30 500,000 20 10 0 0 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3
076
10 30 50 70 90 110 130
075
CODE
10577-
SAMPLE RATE (MSPS)
10577- Figure 39. Input-Referred Noise Histogram; fSAMPLE = 125 MSPS Figure 42. SNR/SFDR vs. Sample Rate; fIN = 70 MHz, fSAMPLE = 125 MSPS
90 DRVDD 80 70 60 B) d 50 AVDD RR ( S 40 P 30 20 10 0 1 10
077
FREQUENCY (MHz)
10577- Figure 40. PSRR vs. Frequency; fCLK = 125 MHz, fSAMPLE = 125 MSPS Rev. B | Page 17 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9635-80 AD9635-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE