Datasheet ADAS3023 (Analog Devices) - 21

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ADAS3023 Data Sheet tCYC TRANSFER FUNCTIONS tCONV tACQ
The ideal transfer characteristic for the ADAS3023 is shown in
CNV
Figure 37. The inputs are configured for differential input ranges and the data outputs are in twos complement format, as listed in 008
PHASE CONVERSION ACQUISITION
Table 6. 10942- Figure 36. System Timing
TWOS STRAIGHT COMPLEMENT BINARY
Regardless of the type of signal, (single-ended symmetric or
011...111 111...111
asymmetric), the ADAS3023 converts all signals present on the
011...110 111...110
enabled inputs and COM pin in a differential fashion identical
011...101 111...101
to an industry-standard difference or instrumentation amplifier.
DE
The conversion results are available after the conversion is complete and can be read back at any time before the end of the next con-
ADC CO
version. Avoid reading back data during the quiet period, indicated by BUSY/SDO2 being active high. Because the ADAS3023 has
100...010 000...010
an on-board conversion clock, the serial clock (SCK) is not
100...001 000...001
required for the conversion process; it is only required to
100...000 000...000
present results to the user.
–FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB
009
ANALOG INPUT
10942- Figure 37. ADC Ideal Transfer Function
Table 6. Output Codes and Ideal Input Voltages Digital Output Code Description Differential Analog Inputs, VREF = 4.096 V (Twos Complement Hex)
FSR − 1 LSB (32,767 × VREF)/(32,768 × PGIA gain) 0x7FFF Midscale + 1 LSB (VREF/(32,768 × PGIA gain)) 0x0001 Midscale 0 0x0000 Midscale − 1 LSB −(VREF/(32,768 × PGIA gain)) 0xFFFF −FSR + 1 LSB −(32,767 × VREF)/(32,768 × PGIA gain) 0x8001 −FSR −VREF × PGIA gain 0x8000 Rev. A | Page 20 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide