Datasheet AD7768, AD7768-4 (Analog Devices) - 93

Data Sheet AD7768/AD7768-4 Bits Bit Name Settings Description Reset Access
1 RAM_BIST_PASS BIST pass/fail. RAM BIST result status. This bit indicates the result of the 0x0 R most recent RAM BIST. The result is latched to this register and is only cleared by a device reset. 0 BIST failed or not run. 1 BIST passed. 0 RAM_BIST_RUNNING BIST status. Reading back the value of this bit allows the user to poll 0x0 R when the BIST test has finished. 0 BIST not running. 1 BIST running.
REVISION IDENTIFICATION REGISTER Address: 0x0A, Reset: 0x06, Name: Revision ID Table 74. Bit Descriptions for Revision ID Bits Bit Name Description Reset Access
[7:0] REVISION_ID ASIC revision. 8-bit ID for revision details. 0x06 R
GPIO CONTROL REGISTER Address: 0x0E, Reset: 0x00, Name: GPIO Control Table 75. Bit Descriptions for GPIO Control Bits Bit Name Setting Description Reset Access
7 UGPIO_ENABLE User GPIO enable. The GPIOx pins are dual-purpose and can be operated only 0x0 RW when the device is in SPI control mode. By default, when the AD7768-4 are powered up in SPI control mode, the GPIOx pins are disabled. This bit is a universal enable/ disable for all GPIOx input/outputs. The direction of each general- purpose pin is determined by Bits[4:0] of this register. 0 GPIO Disabled. 1 GPIO Enabled. 4 GPIOE4_FILTER GPIO4 Direction. This bit assigns the direction of GPIO4 as either an input or an 0x0 RW output. For SPI control, GPIO4 maps to Pin 11, which is the FILTER/GPIO4 pin. 0 Input. 1 Output. 3 GPIOE3_MODE3 GPIO3 Direction. This bit assigns the direction of GPIO3 as either an input or 0x0 RW an output. For SPI control, GPIO3 maps to Pin 15, which is the MODE3/GPIO3 pin. 0 Input. 1 Output. 2 GPIOE2_MODE2 GPIO2 Direction. This bit assigns the direction of GPIO2 as either an input or an 0x0 RW output. For SPI control, GPIO2 maps to Pin 14, which is the MODE2/GPIO2 pin. 0 Input. 1 Output. 1 GPIOE1_MODE1 GPIO1 Direction. This bit assigns the direction of GPIO1 as either an input or an 0x0 RW output. For SPI control, GPIO1 maps to Pin 13, which is the MODE1/GPIO1 pin. 0 Input. 1 Output. 0 GPIO0_MODE0 GPIO0 Direction. This bit assigns the direction of GPIO0 as either an input or 0x0 RW an output. For SPI control, GPIO0 maps to Pin 12, which is the MODE0/GPIO0 pin. 0 Input. 1 Output. Rev. A | Page 93 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE