Datasheet AD4001, AD4005 (Analog Devices)

HerstellerAnalog Devices
Beschreibung16-Bit, 1 MSPS, Precision, Differential SAR ADC
Seiten / Seite37 / 1 — 16-Bit, 2 MSPS/1 MSPS,. Precision, Differential SAR ADCs. Data Sheet. …
RevisionB
Dateiformat / GrößePDF / 920 Kb
DokumentenspracheEnglisch

16-Bit, 2 MSPS/1 MSPS,. Precision, Differential SAR ADCs. Data Sheet. AD4001. /AD4005. FEATURES. GENERAL DESCRIPTION

Datasheet AD4001, AD4005 Analog Devices, Revision: B

Modelllinie für dieses Datenblatt

Textversion des Dokuments

link to page 17
16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs Data Sheet AD4001 /AD4005 FEATURES GENERAL DESCRIPTION Throughput: 2 MSPS/1 MSPS options
The AD4001/AD4005 are low noise, low power, high speed, 16-bit,
INL: ±0.4 LSB maximum
precision successive approximation register (SAR) analog-to-digital
Guaranteed 16-bit no missing codes
converters (ADCs). The AD4001 offers a 2 MSPS throughput, and
Low power
the AD4005 offers a 1 MSPS throughput. They incorporate ease
9.5 mW at 2 MSPS, 4.9 mW at 1 MSPS (VDD only)
of use features that reduce signal chain power consumption,
80 μW at 10 kSPS, 16 mW at 2 MSPS (total)
reduce signal chain complexity, and enable higher channel density.
SNR: 96.2 dB typical at 1 kHz, VREF = 5 V; 95.5 dB typical at 100 kHz
The high-Z mode, coupled with a long acquisition phase,
THD: −123 dB typical at 1 kHz, VREF = 5 V; −99 dB typical at 100 kHz
eliminates the need for a dedicated high power, high speed
Ease of use features reduce system power and complexity
ADC driver, thus broadening the range of low power precision
Input overvoltage clamp circuit
amplifiers that can drive these ADCs directly, while still achieving
Reduced nonlinear input charge kickback
optimum performance. The input span compression feature
High-Z mode
enables the ADC driver amplifier and the ADC to operate off
Long acquisition phase
common supply rails without the need for a negative supply while
Input span compression
preserving the full ADC code range. The low serial peripheral
Fast conversion time allows low SPI clock rates
interface (SPI) clock rate requirement reduces the digital
SPI-programmable modes, read/write capability, status word
input/output power consumption, broadens processor options,
Differential analog input range: ±VREF
and simplifies the task of sending data across digital isolation.
0 V to VREF with VREF from 2.4 V to 5.1 V
Operating from a 1.8 V supply, the AD4001/AD4005 have a ±V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
REF ful y differential input range with V
SAR architecture: no latency/pipeline delay, valid first conversion
REF ranging from 2.4 V to 5.1 V. The AD4001 consumes only 16 mW at 2 MSPS with a minimum
First accurate conversion
SCK rate of 70 MHz in turbo mode, and the AD4005 consumes
Guaranteed operation: −40°C to +125°C
only 8 mW at 1 MSPS. The AD4001/AD4005 both achieve
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
±0.4 LSB integral nonlinearity error (INL) maximum, guaranteed
Ability to daisy-chain multiple ADCs and busy indicator
no missing codes at 16 bits with 96.2 dB typical signal-to-noise
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
ratio (SNR) for 1 kHz inputs. The reference voltage is applied
APPLICATIONS
externally and can be set independently of the supply voltage.
Automatic test equipment
The SPI-compatible, versatile serial interface features seven
Machine automation
different modes including the ability, using the SDI input, to
Medical equipment
daisy-chain several ADCs on a single 3-wire bus, and provides an
Battery-powered equipment
optional busy indicator. The AD4001/AD4005 are compatible with
Precision data acquisition systems
1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD4001/AD4005 are available in a 10-lead MSOP or LFCSP with operation specified from −40°C to +125°C. The devices are pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8).
FUNCTIONAL BLOCK DIAGRAM 2.4V TO 5.1V 1.8V 10µF REF VDD V AD4001/ VIO REF 1.8V TO 5V HIGH-Z V AD4005 TURBO SDI REF/2 MODE MODE 0 IN+ SCK 16-BIT SERIAL 3-WIRE OR 4-WIRE INTERFACE SDO SAR ADC SPI INTERFACE V (DAISY CHAIN, CS) REF IN– STATUS CNV V CLAMP SPAN REF/2 COMPRESSION BITS 0
001
GND
15368- Figure 1.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Applications Information Typical Application Diagrams Analog Inputs Input Overvoltage Clamp Circuit Differential Input Considerations Switched Capacitor Input RC Filter Values Driver Amplifier Choice Single to Differential Driver High Frequency Input Signals Multiplexed Applications Ease of Drive Features Input Span Compression High-Z Mode Long Acquisition Phase Voltage Reference Input Power Supply Digital Interface Register Read/Write Functionality Status Word /CS Mode, 3-Wire Turbo Mode /CS Mode, 3-Wire Without Busy Indicator /CS Mode, 3-Wire with Busy Indicator /CS Mode, 4-Wire Turbo Mode /CS Mode, 4-Wire Without Busy Indicator /CS Mode, 4-Wire with Busy Indicator Daisy-Chain Mode Layout Guidelines Evaluating the AD4001/AD4005 Performance Outline Dimensions Ordering Guide