Datasheet AD9695 (Analog Devices) - 15

AD9695 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS R – + R R _S F F _S E E _S DD1 DD2 DD2 DD1 ND DD1 ND DD1 K– K+ DD1 DD2 DD2 DD1 YSR YSR AV AV AV AV AG S S AV AG AV CL CL AV AV AV AV 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD1 1 48 AVDD1 AVDD1 2 47 AVDD1 AVDD2 3 46 AVDD2 AVDD3 4 45 AVDD3 VIN–A 5 44 VIN–B VIN+A 6 43 VIN+B AVDD3 7 AD9695 42 AVDD3 AVDD2 8 41 AVDD2 TOP VIEW AVDD2 9 (Not to Scale) 40 AVDD2 AVDD2 10 39 AVDD2 DRVDD2 11 38 SPIVDD VREF 12 37 CSB SPIVDD 13 36 SCLK PDWN/STBY 14 35 SDIO DVDD 15 34 DVDD DGND 16 33 DGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 0 A D D N D1 0– 0+ 1– 1+ 2– 2+ 3– 3+ D1 N B G D NB– NB+ T T T T T T T T D G IO_ V U U U U U U U U CI V IO_ DR NCI N O O O O O O O O D D D D D D D D DR /GP DR Y Y DR S S R R R R R R R R /GP _A SE SE SE SE SE SE SE SE _B FD FD NOTES
005
1. ANALOG GROUND. CONNECT THE EXPOSED PAD TO THE ANALOG GROUND PLANE.
15660- Figure 5. Pin Configuration (Top View)
Table 9. Pin Function Descriptions Pin No. Mnemonic Type Description
1, 2, 47 to 49, 52, AVDD1 Power supply Analog Power Supply (0.95 V Nominal). 55, 61, 64 3, 8 to 10, 39 to 41, AVDD2 Power supply Analog Power Supply (1.8 V Nominal). 46, 50, 51, 62, 63 4, 7, 42, 45 AVDD3 Power supply Analog Power Supply (2.5 V Nominal). 5, 6 VIN−A, VIN+A Analog input ADC A Analog Input Complement/True. 11 DRVDD2 Power supply Digital Driver Power Supply (1.8 V Nominal). 12 VREF Input/output Reference Voltage Input (0.50 V)/Do Not Connect. This pin is configurable through the SPI as a no connect pin or as an input. Do not connect this pin if using the internal reference. This pin requires a 0.50 V reference voltage input if using an external voltage reference source. 13, 38 SPIVDD Power supply Digital Power Supply for SPI (1.8 V Nominal). 14 PDWN/STBY Digital control input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby. 15, 34 DVDD Power supply Digital Power Supply (0.95 V Nominal). 16, 33 DGND Ground power Digital Control Ground Supply. These pins connect to the digital ground plane. supply 17 FD_A/GPIO_A0 CMOS output Fast Detect Output for Channel A (FD_A). General-purpose input/output (GPIO) Pin A0 (GPIO_A0). 32 FD_B/GPIO_B0 CMOS output Fast Detect Output for Channel B (FD_B). GPIO Pin B0 (GPIO_B0). 18, 31 DRGND Ground power Digital Driver Ground Supply. This pin connects to the digital driver ground supply plane. 19, 30 DRVDD1 Power supply Digital Driver Power Supply (0.95 V Nominal). 20 SYNCINB− Digital input Active Low JESD204B LVDS/CMOS Sync Input True. 21 SYNCINB+ Digital input Active Low JESD204B LVDS Sync Input Complement. 22, 23 SERDOUT0−, Data output Lane 0 Output Data Complement/True. SERDOUT0+ 24, 25 SERDOUT1−, Data output Lane 1 Output Data Complement/True. SERDOUT1+ Rev. 0 | Page 14 of 135 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS—1300 MSPS AC SPECIFICATIONS—625 MSPS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 1300 MSPS 625 MSPS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Absolute Maximum Input Swing Dither VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls Deemphasis Phase-Locked Loop (PLL) SETTING UP THEAD9695 DIGITAL INTERFACE Example Setup 1—Full Bandwidth Mode Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTERS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE