Datasheet LTC3588-1 (Analog Devices) - 9

HerstellerAnalog Devices
BeschreibungNanopower Energy Harvesting Power Supply
Seiten / Seite20 / 9 — OPERATION. Table 1. Output Voltage Selection. VOUT. VOUT QUIESCENT …
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OPERATION. Table 1. Output Voltage Selection. VOUT. VOUT QUIESCENT CURRENT (IVOUT). Power Good Comparator

OPERATION Table 1 Output Voltage Selection VOUT VOUT QUIESCENT CURRENT (IVOUT) Power Good Comparator

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LTC3588-1
OPERATION
before the output voltage reaches regulation, the buck
Table 1. Output Voltage Selection
converter will shut off and will not be turned on until the
D1 D0 VOUT VOUT QUIESCENT CURRENT (IVOUT)
input voltage again rises above the UVLO rising threshold. 0 0 1.8V 44nA During this time the output voltage will be loaded by less 0 1 2.5V 62nA than 100nA. When the buck brings the output voltage into 1 0 3.3V 81nA regulation the converter enters a low quiescent current 1 1 3.6V 89nA sleep state that monitors the output voltage with a sleep comparator. During this operating mode load current is The internal feedback network draws a small amount of provided by the buck output capacitor. When the output current from VOUT as listed in Table 1. voltage falls below the regulation point the buck regulator
Power Good Comparator
wakes up and the cycle repeats. This hysteretic method of providing a regulated output reduces losses associated A power good comparator produces a logic high referenced with FET switching and maintains an output at light loads. to VOUT on the PGOOD pin the first time the converter The buck delivers a minimum of 100mA of average load reaches the sleep threshold of the programmed VOUT, current when it is switching. signaling that the output is in regulation. The PGOOD pin will remain high until V When the sleep comparator signals that the output has OUT falls to 92% of the desired regulation voltage. Several sleep cycles may occur during reached the sleep threshold the buck converter may be this time. Additionally, if PGOOD is high and V in the middle of a cycle with current still flowing through IN falls below the UVLO falling threshold, PGOOD will remain high until the inductor. Normally both synchronous switches would V turn off and the current in the inductor would freewheel OUT falls to 92% of the desired regulation point. This allows output energy to be used even if the input is lost. to zero through the NMOS body diode. The LTC3588-1 Figure 2 shows the behavior for V keeps the NMOS switch on during this time to prevent the OUT = 3.6V and no load. At t = 75s V conduction loss that would occur in the diode if the NMOS IN becomes high impedance and is discharged by the quiescent current of the LTC3588-1 and through were off. If the PMOS is on when the sleep comparator servicing V trips the NMOS will turn on immediately in order to ramp OUT which is discharged by its own leakage current. V down the current. If the NMOS is on it will be kept on until IN crosses UVLO falling but PGOOD remains high until V the current reaches zero. OUT decreases to 92% of the desired regulation point. The PGOOD pin is designed to drive a microprocessor or Though the quiescent current when the buck is switching other chip I/O and is not intended to drive higher current is much greater than the sleep quiescent current, it is still loads such as an LED. a small percentage of the average inductor current which results in high efficiency over most load conditions. The 6 buck operates only when sufficient energy has been ac- CVIN = CVOUT = 100µF cumulated in the input capacitor and the length of time the 5 VIN converter needs to transfer energy to the output is much 4 V less than the time it takes to accumulate energy. Thus, the IN = UVLO FALLING VOUT buck operating quiescent current is averaged over a long 3 TAGE (V) period of time so that the total average quiescent current VOL is low. This feature accommodates sources that harvest 2 PGOOD small amounts of ambient energy. 1 Four selectable voltages are available by tying the output 0 select bits, D0 and D1, to GND or V 0 100 200 300 IN2. Table 1 shows the TIME (s) four D0/D1 codes and their corresponding output voltages. 35881 F02
Figure 2. PGOOD Operation During Transition to UVLO
35881fc For more information www.linear.com/LTC3588-1 9 Document Outline Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Pin Functions Operation Applications Information Typical Application Related Parts