Datasheet LTC3775 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | High Frequency Synchronous Step-Down Voltage Mode DC/DC Controller |
| Seiten / Seite | 34 / 8 — PIN FUNCTIONS (QFN/MSOP). ILIMT (Pin 1/Pin 3):. IN (Pin 11/Pin 13):. … |
| Dateiformat / Größe | PDF / 553 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS (QFN/MSOP). ILIMT (Pin 1/Pin 3):. IN (Pin 11/Pin 13):. ILIMB (Pin 2/Pin 4):. SW (Pin 12/Pin 14):
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LTC3775
PIN FUNCTIONS (QFN/MSOP) ILIMT (Pin 1/Pin 3):
Topside Current Limit Set Point. This pin can be connected to a sense resistor at the drain of pin has an internal 100μA pull-down current, allowing the top MOSFET for more accurate current limit. the topside current limit threshold to be programmed by
V
an external resistor connected to V
IN (Pin 11/Pin 13):
Main Input Supply. Bypass this pin IN. See Current Limit to PGND with a low ESR ceramic capacitor of value 1μF Applications. or greater (X5R or better).
ILIMB (Pin 2/Pin 4):
Bottom Side Current Limit Set Point.
SW (Pin 12/Pin 14):
Switch Node. Connect this pin to the This pin has an internal 10μA pull-up current, allowing source of the upper power MOSFET. This pin is also used the bottom side current limit threshold to be programmed as the input to the bottom side current limit comparator by an external resistor connected to SGND. See Current and the zero-crossing reverse current comparator. Limit Applications.
TG (Pin 13/Pin 15):
Top Gate Drive. This pin drives the
FB (Pin 3/Pin 5):
Error Amplifi er Input. The FB pin is gate of the top N-channel MOSFET. The TG driver draws connected to a resistive divider from VOUT to SGND. The power from the BOOST pin and returns to the SW pin, feedback loop compensation network is also connected providing true fl oating drive to the top MOSFET. to this pin.
BOOST (Pin 14/Pin 16):
Top Gate Driver Supply. This pin
COMP (Pin 4/Pin 6):
Error Amplifi er Output. Use an RC should be decoupled to SW with a 0.1μF low ESR ceramic network between the COMP pin and the FB pin to compen- capacitor. An external Schottky diode from INTV sate the feedback loop for optimum transient response. CC to BOOST creates a fl oating charge-pump supply at BOOST.
SS (Pin 5/Pin 7):
Soft-Start. Connect this pin to an external No other external supplies are required. capacitor, CSS, to implement a soft-start function. When
MODE/SYNC (Pin 15/Pin 1):
Pulse-Skipping Mode Enable/ the voltage on the SS pin is less than the 0.6V internal Sync Pin. This multifunction pin provides pulse-skipping reference, the LTC3775 regulates the VFB voltage to the mode enable/disable control and an external clock input SS pin voltage instead of the 0.6V reference. for synchronization of the internal oscillator. Pulling this pin
FREQ (Pin 6/Pin 8):
Frequency Set. A resistor connected below 1.2V (DC) or driving it with an external logic-level syn- from this pin to SGND sets the free-running frequency of chronization signal disables pulse-skipping mode operation the internal oscillator. See Applications Information section and forces continuous operation. Pulling the pin above 1.2V for resistor value selection details. enables pulse-skipping mode operation. This pin has an internal 50k pull-down resistor connected to SGND.
SGND (Pin 7/Pin 9):
Signal Ground. All the internal low power circuitry returns to the SGND pin. All feedback and
RUN/SHDN (Pin 16/Pin 2):
Enable/Shutdown Input. Pull- soft-start connections should return to SGND. SGND should ing this pin above 1.22V enables the controller. Forcing be Kelvin connected to a single point near the negative this pin below 1.22V causes the driver outputs to pull terminal of the VOUT bypass capacitor. low. Pulling this pin below 0.74V forces the LTC3775 into shutdown mode. While in shutdown, the INTV
BG (Pin 8/Pin 10):
Bottom Gate Drive. This pin drives the CC regulator and most internal circuitry turns off and the supply current gate of the bottom N-channel synchronous switch MOSFET. drops below 14μA. This pin has an internal 1μA pull-up This pin swings from PGND to INTVCC. current that allows the LTC3775 to power up if this pin is
INTVCC (Pin 9/Pin 11):
Internal 5.2V Regulator Output. left fl oating. The gate driver and control circuits are powered from this
PGND (Exposed Pad Pin 17/Exposed Pad Pin 17):
Power voltage. Bypass this pin to power ground with a low ESR ce- Ground. The BG driver returns to this pin. Connect PGND ramic capacitor of value 4.7μF or greater (X5R or better). to the source of the bottom power MOSFET and the VIN
SENSE (Pin 10/Pin 12):
Topside Current Sensing Input. and INTVCC bypass capacitors. PGND is electrically iso- Connect this pin to the switch node of the converter for lated from SGND. The exposed pad of the QFN and MSOP top MOSFET RDS(ON) current sensing. Alternatively, this packages is connected to PGND. 3775fa 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
PIN FUNCTIONS (QFN/MSOP) ILIMT (Pin 1/Pin 3):
Topside Current Limit Set Point. This pin can be connected to a sense resistor at the drain of pin has an internal 100μA pull-down current, allowing the top MOSFET for more accurate current limit. the topside current limit threshold to be programmed by
V
an external resistor connected to V
IN (Pin 11/Pin 13):
Main Input Supply. Bypass this pin IN. See Current Limit to PGND with a low ESR ceramic capacitor of value 1μF Applications. or greater (X5R or better).
ILIMB (Pin 2/Pin 4):
Bottom Side Current Limit Set Point.
SW (Pin 12/Pin 14):
Switch Node. Connect this pin to the This pin has an internal 10μA pull-up current, allowing source of the upper power MOSFET. This pin is also used the bottom side current limit threshold to be programmed as the input to the bottom side current limit comparator by an external resistor connected to SGND. See Current and the zero-crossing reverse current comparator. Limit Applications.
TG (Pin 13/Pin 15):
Top Gate Drive. This pin drives the
FB (Pin 3/Pin 5):
Error Amplifi er Input. The FB pin is gate of the top N-channel MOSFET. The TG driver draws connected to a resistive divider from VOUT to SGND. The power from the BOOST pin and returns to the SW pin, feedback loop compensation network is also connected providing true fl oating drive to the top MOSFET. to this pin.
BOOST (Pin 14/Pin 16):
Top Gate Driver Supply. This pin
COMP (Pin 4/Pin 6):
Error Amplifi er Output. Use an RC should be decoupled to SW with a 0.1μF low ESR ceramic network between the COMP pin and the FB pin to compen- capacitor. An external Schottky diode from INTV sate the feedback loop for optimum transient response. CC to BOOST creates a fl oating charge-pump supply at BOOST.
SS (Pin 5/Pin 7):
Soft-Start. Connect this pin to an external No other external supplies are required. capacitor, CSS, to implement a soft-start function. When
MODE/SYNC (Pin 15/Pin 1):
Pulse-Skipping Mode Enable/ the voltage on the SS pin is less than the 0.6V internal Sync Pin. This multifunction pin provides pulse-skipping reference, the LTC3775 regulates the VFB voltage to the mode enable/disable control and an external clock input SS pin voltage instead of the 0.6V reference. for synchronization of the internal oscillator. Pulling this pin
FREQ (Pin 6/Pin 8):
Frequency Set. A resistor connected below 1.2V (DC) or driving it with an external logic-level syn- from this pin to SGND sets the free-running frequency of chronization signal disables pulse-skipping mode operation the internal oscillator. See Applications Information section and forces continuous operation. Pulling the pin above 1.2V for resistor value selection details. enables pulse-skipping mode operation. This pin has an internal 50k pull-down resistor connected to SGND.
SGND (Pin 7/Pin 9):
Signal Ground. All the internal low power circuitry returns to the SGND pin. All feedback and
RUN/SHDN (Pin 16/Pin 2):
Enable/Shutdown Input. Pull- soft-start connections should return to SGND. SGND should ing this pin above 1.22V enables the controller. Forcing be Kelvin connected to a single point near the negative this pin below 1.22V causes the driver outputs to pull terminal of the VOUT bypass capacitor. low. Pulling this pin below 0.74V forces the LTC3775 into shutdown mode. While in shutdown, the INTV
BG (Pin 8/Pin 10):
Bottom Gate Drive. This pin drives the CC regulator and most internal circuitry turns off and the supply current gate of the bottom N-channel synchronous switch MOSFET. drops below 14μA. This pin has an internal 1μA pull-up This pin swings from PGND to INTVCC. current that allows the LTC3775 to power up if this pin is
INTVCC (Pin 9/Pin 11):
Internal 5.2V Regulator Output. left fl oating. The gate driver and control circuits are powered from this
PGND (Exposed Pad Pin 17/Exposed Pad Pin 17):
Power voltage. Bypass this pin to power ground with a low ESR ce- Ground. The BG driver returns to this pin. Connect PGND ramic capacitor of value 4.7μF or greater (X5R or better). to the source of the bottom power MOSFET and the VIN
SENSE (Pin 10/Pin 12):
Topside Current Sensing Input. and INTVCC bypass capacitors. PGND is electrically iso- Connect this pin to the switch node of the converter for lated from SGND. The exposed pad of the QFN and MSOP top MOSFET RDS(ON) current sensing. Alternatively, this packages is connected to PGND. 3775fa 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS