Datasheet LTC3729 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | 550kHz, PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator |
| Seiten / Seite | 30 / 8 — PIN FUNCTIONS G Package/UH Package RUN/SS (Pin 1/Pin 28):. VDIFFOUT (Pin … |
| Dateiformat / Größe | PDF / 356 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS G Package/UH Package RUN/SS (Pin 1/Pin 28):. VDIFFOUT (Pin 10/Pin 7):. V –, V + (Pins 11, 12/Pins 8, 9):
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LTC3729
PIN FUNCTIONS G Package/UH Package RUN/SS (Pin 1/Pin 28):
Combination of Soft‑Start, Run
VDIFFOUT (Pin 10/Pin 7):
Output of a Differential Amplifier Control Input and Short‑Circuit Detection Timer. A capaci‑ that provides true remote output voltage sensing. This pin tor to ground at this pin sets the ramp time to full current normally drives an external resistive divider that sets the output. Forcing this pin below 0.8V causes the IC to shut output voltage. down all internal circuitry. All functions are disabled in
V –, V + (Pins 11, 12/Pins 8, 9):
Inputs to an Operational shutdown.
OS OS
Amplifier. Internal precision resistors capable of being
SENSE1+, SENSE2+ (Pins 2,14/Pins 30, 12):
The (+) electronically switched in or out can configure it as a dif‑ Input to the Differential Current Comparators. The ITH ferential amplifier or an uncommitted Op Amp. pin voltage and built‑in offsets between SENSE– and
PGOOD (Pin 15/Pin 13):
Open‑Drain Logic Output. PGOOD SENSE+ pins in conjunction with RSENSE set the current is pulled to ground when the voltage on the EAIN pin is trip threshold. not within ±7.5% of its set point.
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11):
The (–)
TG2, TG1 (Pins 16, 27/Pins 14, 26):
High Current Gate Input to the Differential Current Comparators. Drives for Top N‑Channel MOSFETS. These are the outputs
EAIN (Pin 4/Pin 1):
Input to the Error Amplifier that com‑ of floating drivers with a voltage swing equal to INTVCC pares the feedback voltage to the internal 0.8V reference superimposed on the switch node voltage SW. voltage. This pin is normally connected to a resistive divider
SW2, SW1 (Pins 17, 26/Pins 15, 25):
Switch Node from the output of the differential amplifier (DIFFOUT). Connections to Inductors. Voltage swing at these pins
PLLFLTR (Pin 5/Pin 2):
The Phase‑Locked Loop’s Low is from a Schottky diode (external) voltage drop below Pass Filter is tied to this pin. Alternatively, this pin can ground to VIN. be driven with an AC or DC voltage source to vary the
BOOST2, BOOST1 (Pins 18, 25/Pins 17, 24):
Bootstrapped frequency of the internal oscillator. Supplies to the Topside Floating Drivers. Capacitors
PLLIN (Pin 6/Pin 3):
External Synchronization Input to are connected between the Boost and Switch pins and Phase Detector. This pin is internally terminated to SGND Schottky diodes are tied between the Boost and INTVCC with 50kΩ. The phase‑locked loop will force the rising pins. Voltage swing at the Boost pins is from INTVCC to top gate signal of controller 1 to be synchronized with (VIN + INTVCC). the rising edge of the PLLIN signal.
BG2, BG1 (Pins 19, 23/Pins 18, 22):
High Current Gate
PHASMD (Pin 7/Pin 4):
Control Input to Phase Selector Drives for Bottom Synchronous N‑Channel MOSFETS. which determines the phase relationships between control‑ Voltage swing at these pins is from ground to INTVCC. ler 1, controller 2 and the CLKOUT signal.
PGND (Pin 20/Pin 19):
Driver Power Ground. Connect
ITH (Pin 8/Pin 5):
Error Amplifier Output and Switching to sources of bottom N‑channel MOSFETS and the (–) Regulator Compensation Point. Both current comparator’s terminals of CIN. thresholds increase with this control voltage. The normal
INTV
voltage range of this pin is from 0V to 2.4V.
CC (Pin 21/Pin 20):
Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver
SGND (Pin 9/Pin 6):
Signal Ground, common to both con‑ and control circuits are powered from this voltage source. trollers, must be routed separately from the input switched Decouple to power ground with a 1µF ceramic capacitor current ground path to the common (–) terminal(s) of the placed directly adjacent to the IC and minimum of 4.7µF COUT capacitor(s). additional tantalum or other low ESR capacitor. 3729fb 8 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS G Package/UH Package RUN/SS (Pin 1/Pin 28):
Combination of Soft‑Start, Run
VDIFFOUT (Pin 10/Pin 7):
Output of a Differential Amplifier Control Input and Short‑Circuit Detection Timer. A capaci‑ that provides true remote output voltage sensing. This pin tor to ground at this pin sets the ramp time to full current normally drives an external resistive divider that sets the output. Forcing this pin below 0.8V causes the IC to shut output voltage. down all internal circuitry. All functions are disabled in
V –, V + (Pins 11, 12/Pins 8, 9):
Inputs to an Operational shutdown.
OS OS
Amplifier. Internal precision resistors capable of being
SENSE1+, SENSE2+ (Pins 2,14/Pins 30, 12):
The (+) electronically switched in or out can configure it as a dif‑ Input to the Differential Current Comparators. The ITH ferential amplifier or an uncommitted Op Amp. pin voltage and built‑in offsets between SENSE– and
PGOOD (Pin 15/Pin 13):
Open‑Drain Logic Output. PGOOD SENSE+ pins in conjunction with RSENSE set the current is pulled to ground when the voltage on the EAIN pin is trip threshold. not within ±7.5% of its set point.
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11):
The (–)
TG2, TG1 (Pins 16, 27/Pins 14, 26):
High Current Gate Input to the Differential Current Comparators. Drives for Top N‑Channel MOSFETS. These are the outputs
EAIN (Pin 4/Pin 1):
Input to the Error Amplifier that com‑ of floating drivers with a voltage swing equal to INTVCC pares the feedback voltage to the internal 0.8V reference superimposed on the switch node voltage SW. voltage. This pin is normally connected to a resistive divider
SW2, SW1 (Pins 17, 26/Pins 15, 25):
Switch Node from the output of the differential amplifier (DIFFOUT). Connections to Inductors. Voltage swing at these pins
PLLFLTR (Pin 5/Pin 2):
The Phase‑Locked Loop’s Low is from a Schottky diode (external) voltage drop below Pass Filter is tied to this pin. Alternatively, this pin can ground to VIN. be driven with an AC or DC voltage source to vary the
BOOST2, BOOST1 (Pins 18, 25/Pins 17, 24):
Bootstrapped frequency of the internal oscillator. Supplies to the Topside Floating Drivers. Capacitors
PLLIN (Pin 6/Pin 3):
External Synchronization Input to are connected between the Boost and Switch pins and Phase Detector. This pin is internally terminated to SGND Schottky diodes are tied between the Boost and INTVCC with 50kΩ. The phase‑locked loop will force the rising pins. Voltage swing at the Boost pins is from INTVCC to top gate signal of controller 1 to be synchronized with (VIN + INTVCC). the rising edge of the PLLIN signal.
BG2, BG1 (Pins 19, 23/Pins 18, 22):
High Current Gate
PHASMD (Pin 7/Pin 4):
Control Input to Phase Selector Drives for Bottom Synchronous N‑Channel MOSFETS. which determines the phase relationships between control‑ Voltage swing at these pins is from ground to INTVCC. ler 1, controller 2 and the CLKOUT signal.
PGND (Pin 20/Pin 19):
Driver Power Ground. Connect
ITH (Pin 8/Pin 5):
Error Amplifier Output and Switching to sources of bottom N‑channel MOSFETS and the (–) Regulator Compensation Point. Both current comparator’s terminals of CIN. thresholds increase with this control voltage. The normal
INTV
voltage range of this pin is from 0V to 2.4V.
CC (Pin 21/Pin 20):
Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver
SGND (Pin 9/Pin 6):
Signal Ground, common to both con‑ and control circuits are powered from this voltage source. trollers, must be routed separately from the input switched Decouple to power ground with a 1µF ceramic capacitor current ground path to the common (–) terminal(s) of the placed directly adjacent to the IC and minimum of 4.7µF COUT capacitor(s). additional tantalum or other low ESR capacitor. 3729fb 8 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts