Datasheet LT3487 (Analog Devices) - 10

HerstellerAnalog Devices
BeschreibungBoost and Inverting Switching Regulator for CCD Bias
Seiten / Seite16 / 10 — APPLICATIO S I FOR ATIO Setting the Output Voltages. Start Sequencing. …
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APPLICATIO S I FOR ATIO Setting the Output Voltages. Start Sequencing. Soft-Start. Output Disconnect

APPLICATIO S I FOR ATIO Setting the Output Voltages Start Sequencing Soft-Start Output Disconnect

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LT3487
U U W U APPLICATIO S I FOR ATIO Setting the Output Voltages Start Sequencing
The LT3487 has an accurate internal feedback resistor The LT3487 also has internal sequencing circuitry that that is trimmed to set the feedback currents to 25µA for inhibits the negative channel from operating until the each channel. Only one resistor is needed to set the output feedback voltage of the boost channel reaches about 1.1V voltage for each channel. The output voltage can be set (87% of the fi nal voltage), ensuring that the sum of the according to the following formulas: two outputs is always positive. V – 1.23⎞ There are two ways in which the negative channel may R POS 1= ⎛⎝⎜ start up, depending on the size of the soft-start capacitor. µA 25 ⎠⎟ If there is no soft-start capacitor, or a very small capacitor, –V then the negative channel will start up when the positive R NEG 2 = output reaches 87% of its fi nal value. If a large enough µA 25 soft-start capacitor is used, then the RUN/SS voltage will In order to maintain accuracy, high precision resistors are continue to clamp the negative channel past the point preferred (1% is recommended). where the positive channel is in regulation. Figure 3 shows the start-up sequencing without soft-start, with a small
Soft-Start
soft-start capacitor, and a large soft-start capacitor. The LT3487 has a single soft-start control for both chan-
Output Disconnect
nels. The RUN/SS pin is fed by a 1.4μA current source. The soft-start ramp can be programmed by connecting a The output disconnect uses a PNP transistor with circuitry capacitor from the RUN/SS pin to ground. An open-drain that varies the base current such that the transistor is transistor should be used to pull the pin low to shut down consistently at the edge of saturation, thus yielding the the LT3487. Once the transistor stops sinking the 1.4μA, best compromise between VCE(SAT) and low quiescent the capacitor begins to charge. The chip starts up when current. To remain stable, this circuit requires a bypass the RUN/SS pin charges to 160mV. The VCP node voltage capacitor connected between the VPOS pin and the CAP pin follows the RUN/SS voltage as it continues to ramp up or between the VPOS pin and ground. A ceramic capacitor to ensure slow start-up on the positive channel. The VCN with a value of at least 0.1μF is a good choice. Figure 4 node follows the ramp voltage, down a VBE. This ensures shows that the PNP can support load currents of 50mA that the negative channel starts up after the positive, but with a VCE less than 210mV. The disconnect transistor is still has a slow ramping output to avoid large start-up current limited to provide a maximum of 155mA in short currents. circuit. V V V RUN/SS RUN/SS RUN/SS 2V/DIV 2V/DIV 2V/DIV I I IN IN IIN 200mA/DIV 1A/DIV 500mA/DIV VPOS VPOS VPOS 10V/DIV 10V/DIV 10V/DIV VNEG VNEG VNEG 10V/DIV 10V/DIV 10V/DIV 500µs/DIV 3487 F03a 2ms/DIV 3487 F03b 10ms/DIV 3487 F03c
Figure 3a. VRUN/SS, VPOS, VNEG, Figure 3b. VRUN/SS, VPOS, VNEG, Figure 3c. VRUN/SS, VPOS, VNEG, IIN IIN with No Soft-Start Capacitor IIN with a 10nF Soft-Start Capacitor with a 100nF Soft-Start Capacitor
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