Datasheet LT3029 (Analog Devices) - 11

LT3029
pin FuncTions BYP1/BYP2 (Pin 1/Pin 8):
Bypass. Use the BYP1/BYP2 as a battery’s output impedance rises with frequency. A pins to bypass the reference of the LT3029 regulator and bypass capacitor in the range of 1µF to 10µF suffices. The achieve low output noise performance. Internal circuitry LT3029’s design withstands reverse voltages on the IN pins clamps the BYP1/BYP2 pins to ±0.6V (one VBE) from with respect to ground and the OUT pins. In the case of ground. A small capacitor from the corresponding output to a reversed input, which occurs if a battery is plugged in this pin bypasses the reference to lower the output voltage backwards, the LT3029 acts as if a diode is in series with noise. Using a maximum value of 10nF reduces the output its input. No reverse current flows into the LT3029 and no voltage noise to a typical 20µVRMS over a 10Hz to 100kHz reverse voltage appears at the load. The device protects bandwidth. If not used, this pin must be left unconnected. itself and the load.
NC (Pin 2):
No Connect. This pin is not connected to
SHDN1/SHDN2 (Pin 15/Pin 10):
Shutdown. Pulling the any internal circuitry. It may be floated, tied to VIN or tied SHDN1 or SHDN2 pin low puts its corresponding LT3029 to GND. channel into a low power state and turns its output off. The
OUT1/OUT2 (Pins 3, 4/Pins 6, 7):
Output. The outputs SHDN1 and SHDN2 pins are completely independent of supply power to the loads. A minimum 3.3µF output ca- each other, and each SHDN pin only affects operation on pacitor prevents oscillations on each output. Applications its corresponding channel. Drive the SHDN1 and SHDN2 with large output load transients require larger values of pins with either logic or an open collector/drain with pull-up output capacitance to limit peak voltage transients. See resistors. The resistors supply the pull-up current to the the Applications Information section for more on output open collectors/drains and the SHDN1 or SHDN2 current, capacitance and reverse output characteristics. typically less than 1µA. If unused, connect the SHDN1 and SHDN2 to their corresponding IN pins. Each channel will
GND (Pin 5, 17):
Ground. The exposed pad (Pin 17) of be in its low power shutdown state if its corresponding the DFN and MSOP packages is an electrical connection to GND. To ensure proper electrical and thermal perfor- SHDN pin is not connected. mance, solder Pin 17 to the PCB ground and tie directly
ADJ1/ADJ2: (Pin 16/Pin 9)
Adjust Pin. These are the error to Pin 5. Connect the bottom of the output voltage setting amplifier inputs. These pins are internally clamped to ±9V. resistor divider directly to GND (Pin 5) for optimum load A typical input bias current of 30nA flows into the pins regulation performance. (see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature
IN1/IN2 (Pins 13, 14/Pins 11, 12):
Inputs. The IN1/IN2 in the Typical Performance Characteristics section). The pins supply power to each channel. The LT3029 requires ADJ1 and ADJ2 pin voltage is 1.215V referenced to ground a bypass capacitor at the IN1/IN2 pins if located more and the output voltage range is 1.215V to 19.5V. than six inches away from the main input filter capacitor. Include a bypass capacitor in battery-powered circuits, 3029fb For more information www.linear.com/LT3029 11 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Applications Information Package Description Revision History Typical Application Related Parts