Datasheet LTC2461, LTC2463 (Analog Devices) - 10

LTC2461/LTC2463
APPLICATIONS INFORMATION The START and STOP Conditions Output Data Format
A START (S) condition is generated by transitioning SDA After a START condition, the master sends a 7-bit address from HIGH to LOW while SCL is HIGH. The bus is consid- followed by a read request (R) bit. The bit R is 1 for a ered to be busy after the START condition. When the data Read Request. If the 7-bit address matches the LTC2461/ transfer is finished, a STOP (P) condition is generated by LTC2463’s address (0010100 or 1010100, depending on the transitioning SDA from LOW to HIGH while SCL is HIGH. state of the pin A0) the ADC is selected. When the device is The bus is free after a STOP is generated. START and STOP addressed during the conversion state, it does not accept conditions are always generated by the master. the request and issues a NAK by leaving the SDA line HIGH. When the bus is in use, it stays busy if a repeated START If the conversion is complete, the LTC2461/LTC2463 issue (Sr) is generated instead of a STOP condition. The repeated an ACK by pulling the SDA line LOW. START timing is functionally identical to the START and Following the ACK, the LTC2461/LTC2463 can output data. is used for reading from the device before the initiation The data output stream is 16 bits long and is shifted out of a new conversion. on the falling edges of SCL (see Figure 5a).
Data Transferring
The DATA INPUT/OUTPUT state is concluded once all 16 data bits have been read or after a STOP condition. After the START condition, the I2C bus is busy and data transfer can begin between the master and the addressed The LTC2463 (differential input) output code is given by + – slave. Data is transferred over the bus in groups of nine 32768 • (VIN – VIN )/VREF + 32768. The first bit output + bits, one byte followed by one acknowledge (ACK) bit. The by the LTC2463, D15, is the MSB, which is 1 for VIN ≥ – + – master releases the SDA line during the ninth SCL clock VIN and 0 for VIN < VIN . This bit is followed by succes- cycle. The slave device can issue an ACK by pulling SDA sively less significant bits (D14, D13, …) until the LSB is LOW or issue a Not Acknowledge (NAK) by leaving the output by the LTC2463, see Table 1. SDA line HIGH impedance (the external pull-up resistor The LTC2461 (single-ended input) output code is a direct will hold the line HIGH). Change of data only occurs while binary encoded result, see Table 1. the clock line (SCL) is LOW. 1 7 8 9 1 2 3 8 9 1 2 3 8 9 SCL 7-BIT SDA R D15 D14 D13 D8 ADDRESS D7 D6 D5 D0 MSB LSB START BY ACK BY ACK BY NACK BY MASTER LTC2461/LTC2463 MASTER MASTER SLEEP DATA OUTPUT CONVERSION 24613 F05a
Figure 5a. Read Sequence Timing Diagram
24613fa 10 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Applications Information Package Description Electrical Characteristics Analog Inputs Power Requirements I2c Inputs and Outputs I2c Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts