Datasheet LTC2314-14 (Analog Devices) - 10

LTC2314-14
APPLICATIONS INFORMATION Overview
Leading zeros allow the 14-bit data result to be framed The LTC2314-14 is a low noise, high speed, 14-bit succes- with both leading and trailing zeros for timing and data sive approximation register (SAR) ADC. The LTC2314-14 verification. Since the rising edge of SCK will be coincident operates over a wide supply range (2.7V to 5.25V) and with the falling edge of CS, delay t2 is the delay to the first provides a low drift (20ppm/°C maximum), internal refer- falling edge of SCK, which is simply 0.5 • tSCK. Delays t2 ence and reference buffer. The internal reference buffer is (CS falling edge to SCK leading edge) and t10 (16th falling automatically configured to a 2.048V span in low supply SCK edge to CS rising edge) must be observed for Figures range (2.7V to 3.6V) and to a 4.096V span in the high 5, 6 and 7 and any timing implementation in order for the supply range (4.75V to 5.25V). The LTC2314-14 samples conversion process and data readout to occur correctly. at a 4.5Msps rate and supports an 87.5MHz data clock. The user can bring CS high after the 16th falling SCK edge The LTC2314-14 achieves excellent dynamic performance provided that timing delay t10 is observed. Prematurely (77dB SINAD, 85dB THD) while dissipating only 31mW terminating the conversion by bringing CS high before the from a 5V supply at the 4.5Msps conversion rate. 16th falling SCK edge plus delay t10 will cause a loss of The LTC2314-14 outputs the conversion data with one conversion data for that sample. The sample-and-hold is cycle of conversion latency on the SDO pin. The SDO pin placed in sample mode when CS is brought high. As shown output logic levels are supplied by the dedicated OV in Figure 6, a sample rate of 4.5Msps can be achieved on DD supply pin which has a wide supply range (1.71V to 5.25V) the LTC2314-14 by using an 87.5MHz SCK data clock allowing the LTC2314-14 to communicate with 1.8V, 2.5V, and a minimum acquisition time of 40ns which results in 3V or 5V systems. the minimum throughput time (tTHROUGHPUT) of 222ns. Note that the maximum throughput of 4.5Msps can only The LTC2314-14 provides both nap and sleep power-down be achieved with the timing implementation of SCK held modes through serial interface control to reduce power high during acquisition as shown in Figure 6. dissipation during inactive periods. The LTC2314-14 also supports a continuous data clock
Serial Interface
as shown in Figure 7. With a continuous data clock the acquisition time period and conversion time period must The LT2314-14 communicates with microcontrollers, DSPs be designed as an exact integer number of data clock and other external circuitry via a 3-wire interface. A falling periods. Because the minimum acquisition time is not an CS edge starts a conversion and frames the serial data exact multiple of the minimum SCK period, the maximum transfer. SCK provides the conversion clock for the current sample rate for the continuous SCK timing is less than sample and controls the data readout on the SDO pin of 4.5Msps. For example, a 4.375Msps throughput is achieved the previous sample. CS transitioning low clocks out the using exactly 20 data clock periods with the maximum first leading zero and subsequent SCK falling edges clock data clock frequency of 87.5MHz. For this particular case, out the remaining data as shown in Figures 5, 6 and 7 for the acquisition time period and conversion clock period three different timing schemes. Data is serially output MSB are designed as 4 data clock periods (T first through LSB last, followed by trailing zeros if further ACQ = 45.7ns) and 16data clock periods (T SCK falling edges are applied. Figure 5 illustrates that dur- CONV = 182.9ns) respectively, yielding a throughput time of 228.6ns. ing the case where SCK is held low during the acquisition phase, only one leading zero is output. Figures 6 and 7 The following table illustrates the maximum throughput illustrate that for the SCK held high during acquisition or achievable for each of the three timing patterns. Note continuous clocking mode two leading zeros are output. that in order to achieve the maximum throughput rate of 231414fa 10 For more information www.linear.com/LTC2314-14