Datasheet LTC2162, LTC2161, LTC2160 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 65Msps Low Power ADCs |
| Seiten / Seite | 36 / 1 — FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, f. … |
| Dateiformat / Größe | PDF / 671 Kb |
| Dokumentensprache | Englisch |
FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, f. IN = 70MHz and 69MHz
Modelllinie für dieses Datenblatt
- LTC2160CUK#PBF LTC2160CUK#PBF LTC2160CUK#TRPBF LTC2160CUK#TRPBF LTC2160IUK#PBF LTC2160IUK#PBF LTC2160IUK#TRPBF LTC2160IUK#TRPBF
Textversion des Dokuments
LTC2162/LTC2161/LTC2160 16-Bit, 65Msps/ 40Msps/25Msps Low Power ADCs
FeaTures DescripTion
n 77dB SNR The LTC®2162/LTC2161/LTC2160 are sampling 16-bit A/D n 90dB SFDR converters designed for digitizing high frequency, wide n Low Power: 87mW/63mW/45mW dynamic range signals. They are perfect for demanding n Single 1.8V Supply communications applications with AC performance that n CMOS, DDR CMOS, or DDR LVDS Outputs includes 77dB SNR and 90dB spurious free dynamic range n Selectable Input Ranges: 1VP-P to 2VP-P (SFDR). Ultralow jitter of 0.07psRMS al ows undersampling n 550MHz Full Power Bandwidth S/H of IF frequencies with excellent noise performance. n Optional Data Output Randomizer DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is 3.3LSBRMS. n Serial SPI Port for Configuration n 48-Pin (7mm × 7mm) QFN Package The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An optional clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion 2-Tone FFT, f
1.8V 1.8V
IN = 70MHz and 69MHz
VDD OVDD 0 –10 –20 –30 ANALOG 16-BIT S/H INPUT ADC CORE –40 D15 –50 • CMOS –60 OUTPUT • DDR CMOS OR DRIVERS DDR LVDS –70 • D0 OUTPUTS AMPLITUDE (dBFS) –80 –90 125MHz CLOCK –100 CONTROL CLOCK –110 –120 0 10 20 30 FREQUENCY (MHz) 216210 TA01a GND OGND 2162 TA01b 216210f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
FeaTures DescripTion
n 77dB SNR The LTC®2162/LTC2161/LTC2160 are sampling 16-bit A/D n 90dB SFDR converters designed for digitizing high frequency, wide n Low Power: 87mW/63mW/45mW dynamic range signals. They are perfect for demanding n Single 1.8V Supply communications applications with AC performance that n CMOS, DDR CMOS, or DDR LVDS Outputs includes 77dB SNR and 90dB spurious free dynamic range n Selectable Input Ranges: 1VP-P to 2VP-P (SFDR). Ultralow jitter of 0.07psRMS al ows undersampling n 550MHz Full Power Bandwidth S/H of IF frequencies with excellent noise performance. n Optional Data Output Randomizer DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is 3.3LSBRMS. n Serial SPI Port for Configuration n 48-Pin (7mm × 7mm) QFN Package The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An optional clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion 2-Tone FFT, f
1.8V 1.8V
IN = 70MHz and 69MHz
VDD OVDD 0 –10 –20 –30 ANALOG 16-BIT S/H INPUT ADC CORE –40 D15 –50 • CMOS –60 OUTPUT • DDR CMOS OR DRIVERS DDR LVDS –70 • D0 OUTPUTS AMPLITUDE (dBFS) –80 –90 125MHz CLOCK –100 CONTROL CLOCK –110 –120 0 10 20 30 FREQUENCY (MHz) 216210 TA01a GND OGND 2162 TA01b 216210f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts