Datasheet LTC2142-14, LTC2141-14, LTC2140-14 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 65Msps Low Power Dual ADCs |
| Seiten / Seite | 38 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN … |
| Dateiformat / Größe | PDF / 555 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN = 70MHz and 69MHz
Modelllinie für dieses Datenblatt
- LTC2140CUP-14#PBF LTC2140CUP-14#PBF LTC2140CUP-14#TRPBF LTC2140CUP-14#TRPBF LTC2140IUP-14#PBF LTC2140IUP-14#PBF LTC2140IUP-14#TRPBF LTC2140IUP-14#TRPBF
Textversion des Dokuments
LTC2142-14/ LTC2141-14/LTC2140-14 14-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs
FEATURES DESCRIPTION
n Two-Channel Simultaneously Sampling ADC The LTC®2142-14/LTC2141-14/LTC2140-14 are 2-channel n 73.2dB SNR simultaneous sampling 14-bit A/D converters designed n 90dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 95mW/67mW/50mW Total They are perfect for demanding communications applica- 48mW/34mW/25mW per Channel tions with AC performance that includes 73.2dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.08psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 750MHz Full Power Bandwidth S/H DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 1.2LSB n Shutdown and Nap Modes RMS. n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, double n 64-Pin (9mm × 9mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 69MHz
VDD OVDD 0 –10 CH 1 –20 14-BIT D1_13 ANALOG S/H ADC CORE t –30 INPUT t CMOS, t –40 D1_0 DDR CMOS, –50 OR D2_13 DDR LVDS –60 OUTPUT t OUTPUTS –70 CH 2 t DRIVERS 14-BIT t ANALOG S/H AMPLITUDE (dBFS) –80 ADC CORE D2_0 INPUT –90 –100 –110 –120 65MHz CLOCK 0 5 10 15 20 25 30 CLOCK CONTROL FREQUENCY (MHz) 21421014 TA01b 21421014 TA01a GND OGND 21421014fa 1
FEATURES DESCRIPTION
n Two-Channel Simultaneously Sampling ADC The LTC®2142-14/LTC2141-14/LTC2140-14 are 2-channel n 73.2dB SNR simultaneous sampling 14-bit A/D converters designed n 90dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 95mW/67mW/50mW Total They are perfect for demanding communications applica- 48mW/34mW/25mW per Channel tions with AC performance that includes 73.2dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.08psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 750MHz Full Power Bandwidth S/H DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 1.2LSB n Shutdown and Nap Modes RMS. n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, double n 64-Pin (9mm × 9mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 69MHz
VDD OVDD 0 –10 CH 1 –20 14-BIT D1_13 ANALOG S/H ADC CORE t –30 INPUT t CMOS, t –40 D1_0 DDR CMOS, –50 OR D2_13 DDR LVDS –60 OUTPUT t OUTPUTS –70 CH 2 t DRIVERS 14-BIT t ANALOG S/H AMPLITUDE (dBFS) –80 ADC CORE D2_0 INPUT –90 –100 –110 –120 65MHz CLOCK 0 5 10 15 20 25 30 CLOCK CONTROL FREQUENCY (MHz) 21421014 TA01b 21421014 TA01a GND OGND 21421014fa 1