Datasheet LTC2122 (Analog Devices) - 5

LTC2122
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SDI, SCK)
VIH High Level Input Voltage VDD = 1.8V l 1.3 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance (Note 8) 4 pF
LVDS OUTPUTS (OF+, OF–)
VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Common Mode Output Voltage l 1.125 1.25 1.375 V
CML Outputs
VDIFF CML Differential Output Voltage Output Current Set to 10mA 500 mVppd Output Current Set to 12mA 600 mVppd Output Current Set to 14mA 700 mVppd Output Current Set to 16mA 800 mVppd VOH Output High Level Directly-Coupled 50Ω to OVDD OVDD V Directly-Coupled 100Ω Differential OVDD-1/4 VDIFF V AC-Coupled OVDD-1/4 VDIFF V VOL Output Low Level Directly-Coupled 50Ω to OVDD OVDD-1/2 VDIFF V Directly-Coupled 100Ω Differential OVDD-3/4 VDIFF V AC-Coupled OVDD-3/4 VDIFF V VOCM Output Common Mode Level Directly-Coupled 50Ω to OVDD OVDD-1/4 VDIFF V Directly-Coupled 100Ω Differential OVDD-1/2 VDIFF V AC-Coupled OVDD-1/2 VDIFF V ROUT Output Resistance Single-Ended 50 Ω Differential l 80 100 120 Ω
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS, 1/tS Sampling Frequency (Note 9) l 50 170 MHz tL 1× CLK Low Time (Note 8) Duty Cycle Stabilizer Off l 2.79 2.94 10 ns Duty Cycle Stabilizer On l 1.5 2.94 10 ns tH 1× CLK High Time (Note 8) Duty Cycle Stabilizer Off l 2.79 2.94 10 ns Duty Cycle Stabilizer On l 1.5 2.94 10 ns tDCK DEVCLK Period 2X_CLK SPI Register = 0 l 5.88 20 ns 2X_CLK SPI Register = 1 l 2.94 10 ns
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode CSDO = 20pF, RPULLUP = 2kΩ l 250 ns tCSS CS Falling to SCK Rising Set Up Time l 5 ns tSCH SCK Rising to CS Rising Hold Time l 5 ns tSCS SCK Falling to CS Falling Set Up Time l 5 ns 2122fb For more information www.linear.com/LTC2122 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Digital Inputs And Outputs Timing characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions ADC PERFORMANCE TERMS SERIAL INTERFACE TERMS Applications Information CONVERTER OPERATION INPUT DRIVE CIRCUITS GROUNDING AND BYPASSING HEAT TRANSFER Typical Applications Package Description Revision History Typical Application Related Parts