Datasheet LTC1742 (Analog Devices) - 4

HerstellerAnalog Devices
Beschreibung14-Bit, 65Msps Low Noise ADC
Seiten / Seite20 / 4 — DIGITAL I PUTS A D DIGITAL OUTPUTS The. indicates specifications which …
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DokumentenspracheEnglisch

DIGITAL I PUTS A D DIGITAL OUTPUTS The. indicates specifications which apply over the full

DIGITAL I PUTS A D DIGITAL OUTPUTS The indicates specifications which apply over the full

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LTC1742
U U DIGITAL I PUTS A D DIGITAL OUTPUTS The

indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V, MSBINV and OE ● 2.4 V VIL Low Level Input Voltage VDD = 4.75V, MSBINV and OE ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±10 µA CIN Digital Input Capacitance MSBINV and OE Only 1.5 pF VOH High Level Output Voltage OVDD = 4.75V IO = –10µA 4.74 V IO = – 200µA ● 4 4.74 V VOL Low Level Output Voltage OVDD = 4.75V IO = 160µA 0.05 V IO = 1.6mA ● 0.1 0.4 V IOZ Hi-Z Output Leakage D13 to D0 VOUT = 0V to VDD, OE = High ● ±10 µA COZ Hi-Z Output Capacitance D13 to D0 OE = High (Note 8) ● 15 pF ISOURCE Output Source Current VOUT = 0V – 50 mA ISINK Output Sink Current VOUT = 5V 50 mA
W U POWER REQUIRE E TS The

indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage 4.75 5.25 V IDD Positive Supply Current ● 255 275 mA PDIS Power Dissipation ● 1.275 1.375 W OVDD Digital Output Supply Voltage 0.5 VDD V
W U TI I G CHARACTERISTICS The

indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t0 ENC Period (Note 9) ● 15.3 2000 ns t1 ENC High (Note 8) ● 7.3 1000 ns t2 ENC Low (Note 8) ● 7.3 1000 ns t3 Aperture Delay (Note 8) 0 ns t4 ENC to CLKOUT Falling CL = 10pF (Note 8) ● 1 2.4 4 ns t5 ENC to CLKOUT Rising CL = 10pF (Note 8) t1 + t4 ns For 65Msps 50% Duty Cycle CL = 10pF (Note 8) ● 8.7 10.1 11.7 ns t6 ENC to DATA Delay CL = 10pF (Note 8) ● 2 4.9 7.2 ns t7 ENC to DATA Delay (Hold Time) (Note 8) ● 1.4 3.4 4.7 ns t8 ENC to DATA Delay (Setup Time) CL = 10pF (Note 8) t0 – t6 ns For 65Msps 50% Duty Cycle CL = 10pF (Note 8) ● 8.2 10.5 13.4 ns t9 CLKOUT to DATA Delay (Hold Time), (Note 8) ● 7 ns 65Msps 50% Duty Cycle t10 CLKOUT to DATA Delay (Setup Time), CL = 10pF (Note 8) ● 3 ns 65Msps 50% Duty Cycle t11 DATA Access Time After OE CL = 10pF (Note 8) 10 25 ns t12 BUS Relinquish (Note 8) 10 25 ns Data Latency 5 cycles 1742f 4