Datasheet LTC1609 (Analog Devices) - 4

HerstellerAnalog Devices
Beschreibung16-Bit, 200ksps, Serial Sampling ADC with Multiple Input Ranges
Seiten / Seite24 / 4 — DIGITAL I PUTS A D DIGITAL OUTPUTS The. indicates specifications which …
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DokumentenspracheEnglisch

DIGITAL I PUTS A D DIGITAL OUTPUTS The. indicates specifications which apply over the full

DIGITAL I PUTS A D DIGITAL OUTPUTS The indicates specifications which apply over the full

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LTC1609
U U DIGITAL I PUTS A D DIGITAL OUTPUTS The

indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) LTC1609/LTC1609A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V ● 2.4 V VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±10 µA CIN Digital Input Capacitance 5 pF VOH High Level Output Voltage VDD = 4.75V IO = –10µA 4.5 V IO = – 200µA ● 4.0 V VOL Low Level Output Voltage VDD = 4.75V IO = 160µA 0.05 V IO = 1.6mA ● 0.10 0.4 V ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VDD 10 mA
W U TI I G CHARACTERISTICS The

indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) LTC1609/LTC1609A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t1 Convert Pulse Width (Note 11) ● 40 ns t2 R/C, CS to BUSY Delay CL = 25pF ● 80 ns t3 BUSY Low Time ● 3 µs t4 BUSY Delay After End of Conversion 100 ns t5 Aperture Delay 5 ns t6 Conversion Time ● 3 µs t7 Acquisition Time ● 2 µs t6 + t7 Throughput Time ● 5 µs t8 R/C Low to DATACLK Delay 260 ns t9 DATACLK Period 150 ns t10 DATA Valid Setup Time ● 15 ns t11 DATA Valid Hold Time ● 40 ns t12 External DATACLK Period ● 50 ns t13 External DATACLK High ● 20 ns t14 External DATACLK Low ● 20 ns t15 R/C, CS to External DATACLK Setup Time ● 15 t12 ns t16 R/C to CS Setup Time ● 10 ns t17 External DATACLK to SYNC Delay ● 6 50 ns t18 External DATACLK to DATA Valid Delay ● 10 50 ns t19 CS to External DATACLK Rising Edge Delay ● 10 ns t20 Previous DATA Valid After CS, R/C Low (Note 9) ● 2.2 µs t21 BUSY to External DATACLK Setup Time (Note 9) ● 5 ns t22 BUSY Falling Edge to Final External DATACLK (Notes 10, 17) ● 1.2 µs t23 TAG Valid Setup Time ● 0 ns t24 TAG Valid Hold Time ● 15 ns 1609fa 4