Datasheet LTC1274, LTC1277 (Analog Devices) - 5

LTC1274/LTC1277
W U TI I G CHARACTERISTICS (Note 5) See Figures 13 to 17. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t16 HBEN↓ to Low Byte Data Valid CL = 100pF (LTC1277 Only) ● 45 100 ns t17 HBEN↑ to RD↓ Setup Time (Note 10) (LTC1277 Only) ● 10 ns t18 RD↑ to HBEN↓ Setup Time (Note 10) (LTC1277 Only) ● 10 ns The ● denotes specifications which apply over the full operating
Note 8:
For LTC1274, bipolar offset is the offset voltage measured from temperature range; all other limits and typicals TA = 25°C. – 0.5LSB when the output code flickers between 0000 0000 0000 and
Note 1:
Absolute Maximum Ratings are those values beyond which the life 1111 1111 1111. For LTC1277, bipolar offset voltage is measured from of a device may be impaired. – 0.5LSB when the output code flickers between 0111 1111 1111 and
Note 2:
All voltage values are with respect to ground with DGND and 1000 0000 0000. AGND wired together and V
Note 9:
The AC tests apply to bipolar mode only and the S/(N + D) is 71dB LOGIC is tied to VDD in LTC1277 (unless otherwise noted). (typ) for unipolar mode at 100kHz input frequency.
Note 3:
When these pin voltages are taken below V
Note 10:
Guaranteed by design, not subject to test. SS (ground for unipolar mode) or above VDD, they will be clamped by internal diodes. This product
Note 11:
Recommended operating conditions. can handle input currents greater than 60mA below VSS (ground for
Note 12:
AIN must not exceed VDD or fall below VSS by more than 50mV to unipolar mode) or above VDD without latch-up. specified accuracy.
Note 4:
When these pin voltages are taken below VSS (ground for unipolar
Note 13:
The falling CONVST edge starts a conversion. If CONVST returns mode), they will be clamped by internal diodes. This product can handle high at a bit decision point during the conversion it can create small input currents greater than 60mA below VSS (ground for unipolar mode) errors. For best performance ensure that CONVST returns high either without latch-up. These pins are not clamped to VDD. within 400ns after conversion start (i.e., before the first bit decision) or
Note 5:
VDD = 5V (VSS = – 5V for bipolar mode), VLOGIC = VDD (LTC1277), after BUSY rises (i.e., after the last bit test). See timing diagrams Modes fSAMPLE = 100ksps, tr = tf = 5ns unless otherwise specified. 1a and 1b (Figures 13, 14).
Note 6:
Linearity, offset and full-scale specifications apply for unipolar and bipolar modes.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
W U TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity vs Differential Nonlinearity vs ENOBs and S/(N + D) vs Output Code Output Code Input Frequency
1.00 1.00 12 74 f f SAMPLE = 100kHz SAMPLE = 100kHz 11 68 10 NYQUIST 62 FREQUENCY 0.50 0.50 9 56 8 50 S/(N + D)(dB) 7 0 0 6 5 4 –0.50 –0.50 3 2 EFFECTIVE NUMBER OF BITS (ENOBs) INTEGRAL NONLINEARITY ERROR (LSB) 1 fSAMPLE = 100kHz DIFFERENTIAL NONLINEARITY ERROR (LSB) –1.00 –1.00 0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 10k 100k 1M 2M OUTPUT CODE OUTPUT CODE INPUT FREQUENCY (Hz) LT1274/77 • TPC01 LTC1274/77 • TPC03 LT1274/77 • TPC02 5