Datasheet LTC1091, LTC1092, LTC1093, LTC1094 (Analog Devices) - 19
| Hersteller | Analog Devices |
| Beschreibung | 1-, 2-, 6- and 8-Channel, 10-Bit Serial I/O Data Acquisition Systems |
| Seiten / Seite | 32 / 19 — APPLICATI. S I FOR ATIO. Interfacing to the Parallel Port of the. LABEL. … |
| Dateiformat / Größe | PDF / 288 Kb |
| Dokumentensprache | Englisch |
APPLICATI. S I FOR ATIO. Interfacing to the Parallel Port of the. LABEL. MNEMONIC. OPERAND. COMMENTS. Intel 8051 Family
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LTC1091/LTC1092 LTC1093/LTC1094
O U U W U APPLICATI S I FOR ATIO Interfacing to the Parallel Port of the LABEL MNEMONIC OPERAND COMMENTS Intel 8051 Family
MOV A, #FFH DIN Word for LTC1091 SETB P1.4 Make Sure CS Is High The Intel 8051 has been chosen to demonstrate the CLR P1.4 CS Goes Low interface between the LTC1091 and parallel port micro- MOV R4, #04 Load Counter processors. Normally, the CS, SCLK and D LOOP 1 RLC A Rotate D IN signals IN Bit into Carry would be generated on three port lines and the D CLR P1.3 SCLK Goes Low OUT signal MOV P1.2, C Output D read on a 4th port line. This works very well. However, we IN Bit to LTC1091 SETB P1.3 SCLK Goes High will demonstrate here an interface with the DIN and DOUT DJNZ R4, LOOP 1 Next Bit of the LTC1091 tied together as described in section 4. MOV P1, #04 Bit 2 Becomes an Input CLR P1.3 SCLK Goes Low This saves one wire. MOV R4, #09 Load Counter LOOP MOV C, P1.2 Read Data Bit into Carry The 8051 first sends the start bit and MUX address to the RLC A Rotate Data Bit into Acc LTC1091 over the data line connected to P1.2. Then P1.2 SETB P1.3 SCLK Goes High is reconfigured as an input (by writing to it a one) and the CLR P1.3 SCLK Goes Low 8051 reads back the 10-bit A/D result over the same data DJNZ R4, LOOP Next Bit MOV R2, A Store MSBs in R2 line. MOV C, P1.2 Read Data Bit into Carry SETB P1.3 SCLK Goes High CLR P1.3 SCLK Goes Low CS P1.4 CLR A Clear Acc CLK ANALOG P1.3 LTC1091 8051 RLC A Rotate Data Bit from Carry to Acc INPUTS DOUT P1.2 MOV C, P1.2 Read Data Bit into Carry DIN MUX ADDRESS RRC A Rotate Right into Acc 1091-4 AI17 A/D RESULT RRC A Rotate Right into Acc MOV R3, A Store LSBs in R3
DOUT from LTC1091 Stored in 8051 RAM
SETB P1.4 CS Goes High MSB R2 B9 B8 B7 B6 B5 B4 B3 B2 LSB R3 B1 B0 0 0 0 0 0 0 MSBF BIT LATCHED INTO LTC1091 CS 1 2 3 4 CLK SGL/ DATA (D ODD/ IN/DOUT) START MSBF B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DIFF SIGN 1091/2/3/4 AI18 8051 P1.2 OUTPUTS LTC1091 SENDS A/D RESULT DATA TO LTC1091 BACK TO 8051 P1.2 8051 P1.2 RECONFIGURED AS AN LTC1091 TAKES CONTROL OF DATA LINE INPUT AFTER THE 4TH RISING CLK ON 4TH FALLING CLK AND BEFORE THE 4TH FALLING CLK 19
O U U W U APPLICATI S I FOR ATIO Interfacing to the Parallel Port of the LABEL MNEMONIC OPERAND COMMENTS Intel 8051 Family
MOV A, #FFH DIN Word for LTC1091 SETB P1.4 Make Sure CS Is High The Intel 8051 has been chosen to demonstrate the CLR P1.4 CS Goes Low interface between the LTC1091 and parallel port micro- MOV R4, #04 Load Counter processors. Normally, the CS, SCLK and D LOOP 1 RLC A Rotate D IN signals IN Bit into Carry would be generated on three port lines and the D CLR P1.3 SCLK Goes Low OUT signal MOV P1.2, C Output D read on a 4th port line. This works very well. However, we IN Bit to LTC1091 SETB P1.3 SCLK Goes High will demonstrate here an interface with the DIN and DOUT DJNZ R4, LOOP 1 Next Bit of the LTC1091 tied together as described in section 4. MOV P1, #04 Bit 2 Becomes an Input CLR P1.3 SCLK Goes Low This saves one wire. MOV R4, #09 Load Counter LOOP MOV C, P1.2 Read Data Bit into Carry The 8051 first sends the start bit and MUX address to the RLC A Rotate Data Bit into Acc LTC1091 over the data line connected to P1.2. Then P1.2 SETB P1.3 SCLK Goes High is reconfigured as an input (by writing to it a one) and the CLR P1.3 SCLK Goes Low 8051 reads back the 10-bit A/D result over the same data DJNZ R4, LOOP Next Bit MOV R2, A Store MSBs in R2 line. MOV C, P1.2 Read Data Bit into Carry SETB P1.3 SCLK Goes High CLR P1.3 SCLK Goes Low CS P1.4 CLR A Clear Acc CLK ANALOG P1.3 LTC1091 8051 RLC A Rotate Data Bit from Carry to Acc INPUTS DOUT P1.2 MOV C, P1.2 Read Data Bit into Carry DIN MUX ADDRESS RRC A Rotate Right into Acc 1091-4 AI17 A/D RESULT RRC A Rotate Right into Acc MOV R3, A Store LSBs in R3
DOUT from LTC1091 Stored in 8051 RAM
SETB P1.4 CS Goes High MSB R2 B9 B8 B7 B6 B5 B4 B3 B2 LSB R3 B1 B0 0 0 0 0 0 0 MSBF BIT LATCHED INTO LTC1091 CS 1 2 3 4 CLK SGL/ DATA (D ODD/ IN/DOUT) START MSBF B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DIFF SIGN 1091/2/3/4 AI18 8051 P1.2 OUTPUTS LTC1091 SENDS A/D RESULT DATA TO LTC1091 BACK TO 8051 P1.2 8051 P1.2 RECONFIGURED AS AN LTC1091 TAKES CONTROL OF DATA LINE INPUT AFTER THE 4TH RISING CLK ON 4TH FALLING CLK AND BEFORE THE 4TH FALLING CLK 19