1.2 GHz Clock Distribution IC, PLL Core,
Dividers, Delay Adjust, Five Outputs
AD9511
FEATURES FUNCTIONAL BLOCK DIAGRAM
VS Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure GENERAL DESCRIPTION
The AD9511 provides a multi-output clock distribution
function along with an on-chip PLL core. The design
emphasizes low jitter and phase noise to maximize data
converter performance. Other applications with demanding
phase noise and jitter requirements also benefit from this part.
The PLL section consists of a programmable reference divider
(R); a low noise phase frequency detector (PFD); a precision
charge pump (CP); and a programmable feedback divider (N).
By connecting an external VCXO or VCO to the CLK2/CLK2B
pins, frequencies up to 1.6 GHz may be synchronized to the
input reference.
There are five independent clock outputs. Three outputs are
LVPECL (1.2 GHz), and two are selectable as either LVDS
(800 MHz) or CMOS (250 MHz) levels. CPRSET VCP DISTRIBUTION …