FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency: PLL2_TO1 YES END
1PLL2_TO IS A CALCULATED TIMEOUT VALUE. SEE THE THEORY OF OPERATION, COMPONENT BLOCKS—INPUT PLL (PLL1) FOR ITS FORMULA. Figure 46. AD9523-1 Device Initialization Rev. C | Page 41 of 63 09278-145 YES AD9523-1 Data Sheet
SOFTWARE
GENERATED
AD9523-1 SETUP
FILE START WRITE:
R0x000 TO R0x006 WRITE:
R0x010 TO R0x01D WRITE:
R0x0F0 TO R0x0F9 WRITE:
R0x190 TO R0x1BB WRITE:
R0x230 TO R0x233 WRITE:
R0xA00 TO R0xA16 END 09278-146 WRITE:
R0x234 = 0x01 Figure 47. Subprocess: Write Registers from Setup File Rev. C | Page 42 of 63 Data Sheet AD9523-1 POWER DISSIPATION AND THERMAL CONSIDERATIONS
The AD9523-1 is a multifunctional, high speed device that
targets a wide variety of clock applications. The numerous
innovative features contained in the device each consume
incremental power. If all outputs are enabled in the maximum
frequency and mode that have the highest power, the safe
thermal operating conditions of the device may be exceeded.
Careful analysis and consideration of power dissipation and
thermal management are critical elements in the successful
application of the AD9523-1 device.
The AD9523-1 device is specified to operate within the …