BLDC Motor Controller with 16bit CPU 523.05 PRODUCTION DATA – May 12, 2017 Features General description Gate drive circuit for B6-NMOS bridge IC supply voltage range 7 to 28V (extended 5V to E523.05 is a BLDC motor system-in-a-chip including a
16bit CPU core. It controls 3 NMOS half-bridges for driving BLDC motors, DC motors, or other loads. Small
loads can be driven directly without external FETs.
The IC includes a mean-current measurement and
protects against over-current (programmable threshold),
over-temperature, over-and under-voltages and shortciruits (programmable thresholds for each FET). Two
product versions with a state of the art LIN2.x (compatible down to LIN1.3) or with a bidirectional PWM interface are available. End-of-line programming is possible
via JTAG or high-speed LIN.
Highest performance is provided by a 16bit CPU,
assisted by a coprocessor for PWM waveform generation, which generates an autonomously progressing
waveform. A 2nd coprocessor for ADC tasking automatically collects all analog system information synchronously
to the output PWM. These 3 processing units are optimizing system performance, system reliability, EMC performance, current dissipation and development time.
The system clock is tunable in very fine steps to improve
EMC behaviour. An adjustment of the system clock of a
LIN-master is possible.
E523.05 is suited for all commutation algorithms like
block, sine wave, SVM (space vector modulation) and
FOC (field oriented control). 42V) CPU 16 bit, 4 -48MHz for application tasks 32 kByte FLASH, ECC protected 16 kByte ROM 4 kByte SRAM, parity protected Typical deep-sleep mode current 20ВµA 2nd window watchdog and two independent clocks LIN2.x, LIN1.3 or bidirectional PWM Interface Flashable-via-LIN (high speed) for end-of-line pro gramming
Motor over-current protection with CPU interrupt
6 * FET short-circuit protection on gate driver site
Multiplication(16*16bit) & division(32/16bit) modules
Coprocessor for PWM waveform generation
Coprocessor for ADC tasking …